Patents Examined by Sheela Nadig
  • Patent number: 5450563
    Abstract: The cache system comprises a level one (L1) data cache, a level one (L1) key cache for storing a plurality of access keys for respective pages or blocks of data referenced by the central processor. A level three (L3) storage stores the data requested by the central processor and an access key array including the plurality of access keys. A level two (L2) data cache is coupled between the L3 storage and the L1 data cache and stores a copy of data fetched from the L3 storage for the L1 data cache pursuant to a read request and data written by the central processor. The level two (L2) key cache is coupled between the L3 storage access key array and the L1 key cache and stores the plurality of access keys for respective pages or blocks of data in the L2 data cache.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: September 12, 1995
    Assignee: International Business Machines Corporation
    Inventor: Steven L. Gregor
  • Patent number: 5420999
    Abstract: A computer data storage management system for allocating and releasing data storage memory in response to requests from application programs. The data storage is organized as a plurality of subpools, each subpool containing a control area 21 and a plurality of pages of memory 122, 222, 322 divided into fixed length cells. Free memory cells contain, within the area used for data storage in non-free cells, an indication 182, 183, 382-384. The presence of this indication is checked prior to the allocation of cells and the absence of the indicator prior to release of the cells.
    Type: Grant
    Filed: October 29, 1992
    Date of Patent: May 30, 1995
    Assignee: International Business Machines Corporation
    Inventor: Paul Mundy
  • Patent number: 5418925
    Abstract: A method for reducing the apparent response time for write I/O operations initiated by a host system to a RAID level 3, 4 or 5 disk array including a spare disk drive. The disclosed method comprises the steps of (1) saving write data received by the disk array from the host system directly to the spare drive, (2) issuing a write complete status signal to the host system indicating completion of the host write I/O operation, thus freeing the host processor to perform other functions, and (3) transferring the data saved to the spare drive to the active drives within the array. This third step may be executed at any convenient time following the second step. For example, in systems where a host processor functions as the array controller, this third step may be delayed while higher priority tasks are executed. In systems where the disk array includes an array controller, the array controller coordinates the execution of this third step with other controller or array operations to optimize array operation.
    Type: Grant
    Filed: October 23, 1992
    Date of Patent: May 23, 1995
    Assignee: AT&T Global Information Solutions Company
    Inventors: Robert A. DeMoss, Keith B. DuLac