Abstract: Provided is a light-emitting device that makes it possible to emit, with high efficiency, light having higher uniformity. The light-emitting device includes a light source, a wavelength conversion unit, and a wall member. The light source is disposed on a substrate. The wavelength conversion unit includes a wavelength conversion member and a transparent member that contains the wavelength conversion member therein. The wavelength conversion member is disposed to face the light source in a thickness direction and converts first wavelength light from the light source to second wavelength light. The wall member is provided on a substrate and surrounds the light source in a plane that is orthogonal to the thickness direction. A region occupied by the wavelength conversion member is wider than a region surrounded by the wall member, and entirely overlaps with the region surrounded by the wall member in the thickness direction.

Abstract: A thin film structure includes a substrate; and a material layer having a fluorite structure, the material layer on the substrate and comprising crystals of which <112> crystal orientation is aligned in a normal direction of the substrate. The material layer may have ferroelectricity. The material layer may include the crystals of which the <112> crystal orientation is aligned in the normal direction of the substrate among all crystals of the material layer in a dominant ratio.

Abstract: An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. A ferroelectric layer formed according to the present teaching may be chlorine-free. Structures adjacent the ferroelectric layer are also formed with chlorine-free precursors. The absence of chlorine in the adjacent structures prevents diffusion of chlorine into the ferroelectric layer and prevents the formation of chlorine complexes at interfaces with the ferroelectric layer. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

Abstract: A semiconductor device includes: a first source/drain region; a second source/drain region; a channel between the first source/drain region and the second source/drain region; an interfacial insulating layer on the channel; a ferroelectric layer on the interfacial insulating layer; and a gate electrode on the ferroelectric layer, wherein, when a numerical value of dielectric constant of the interfacial insulating layer is K and a numerical value of remnant polarization of the ferroelectric layer is Pr, a material of the interfacial insulating layer and a material of the ferroelectric layer are selected so that K/Pr is 1 or more.

Abstract: A semiconductor device includes a stack including a plurality of electrode layers and a plurality of interlayer dielectric layers that are alternately stacked in a vertical direction on a substrate; and a plurality of vertical pass transistors disposed over the stack, and each of the plurality of vertical pass transistors coupled to a corresponding electrode layer, wherein the plurality of vertical pass transistors includes a plurality of first vertical pass transistors and a plurality of second vertical pass transistors, and the plurality of second vertical pass transistors are disposed over the plurality of first vertical pass transistors to be staggered with the plurality of first vertical pass transistors.

Abstract: Some embodiments include an integrated assembly having first and second pillars of semiconductor material laterally offset from one another. The pillars have source/drain regions and channel regions vertically offset from the source/drain regions. Gating structures pass across the channel regions, and extend along a first direction. An insulative structure is over regions of the first and second pillars, and extends along a second direction which is crosses the first direction. Bottom electrodes are coupled with the source/drain regions. Leaker-device-structures extend upwardly from the bottom electrodes. Ferroelectric-insulative-material is laterally adjacent to the leaker-device-structures and over the regions of the bottom electrodes. Top-electrode-material is over the ferroelectric-insulative-material and is directly against the leaker-device-structures. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor which includes a source/drain feature adjoining an active region, and a gate stack over the active region. The semiconductor device structure further includes a capacitor above the transistor, the capacitor including a bottom electrode layer on the gate stack and a ferroelectric layer on the bottom electrode layer. The ferroelectric layer is made of a Hf-based dielectric material. The semiconductor device structure further includes gate spacer layers surrounding the gate stack, the bottom electrode layer and the ferroelectric layer.

Abstract: Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.

Abstract: In some embodiments, the present disclosure relates to a 3D memory device, including a plurality of gate lines interleaved between a plurality of dielectric layers in a vertical direction, the plurality of gate lines forming recesses between the plurality of dielectric layers; a source/drain line disposed next to the plurality of dielectric layers, spaced from the plurality of gate lines by the recesses in a lateral direction; a ferroelectric film arranged laterally between sidewalls of the plurality of gate lines and the source/drain line and confined within the recesses; and a semiconductor film disposed within the recesses and spacing the ferroelectric film from the source/drain line.

Abstract: A transistor device and the manufacturing methods are described. The device includes a gate structure having a gate layer and a ferroelectric layer, source and drain terminals, and a crystalline channel portion. The source and drain terminals are disposed at opposite sides of the gate structure. The crystalline channel portion extends between the source and drain terminals. The source and drain terminals are disposed on the crystalline channel portion and the gate structure is disposed on the crystalline channel portion. The crystalline channel portion includes a first material containing a Group III element and a Group V element, the gate layer includes a second material containing a Group III element and a rare-earth element, and the ferroelectric layer includes a third material containing a Group III element, a rare-earth element and a Group V element.

Abstract: The present application discloses a display panel and a manufacturing method thereof. The display panel includes a substrate, a pixel definition layer and a light-emitting layer. The pixel definition layer is disposed on the substrate. The pixel definition layer is provided with a first through hole, the first through hole penetrates through the pixel definition layer, the light-emitting layer is disposed in the first through hole, and an isolation layer is disposed between the light emitting layer and the pixel definition layer.

Abstract: A display substrate has a display region, a peripheral region surrounding the display region, and pad regions on a first connection side of the peripheral region and distal to the display region. The display region includes sub-pixel regions. The display substrate further includes: a base, and organic light-emitting diodes and a first power supply line all on the base. The organic light-emitting diodes are provided in the sub-pixel regions, respectively. A cathode of each organic light-emitting diode extends from the display region to the peripheral region and is connected to the first power supply line in the peripheral region. The first connection side includes a first connection region corresponding to a position between two adjacent pad regions, and a second connection region other than the first connection region. A connection region between the first power supply line and the cathode covers at least part of the second connection region.

Abstract: An integration manufacturing method of a depletion high voltage NMOS device and a depletion low voltage NMOS device includes: providing a substrate; forming a semiconductor layer on the substrate; forming insulation regions on the semiconductor layer; forming an N-type well in the depletion high voltage NMOS device region; forming a high voltage P-type well in the semiconductor layer, wherein the N-type well and the high voltage P-type well are in contact with each other in a channel direction; forming an oxide layer on the semiconductor layer after the N-type well and the high voltage P-type well formed; forming a low voltage P-type well; and forming an N-type high voltage channel region and an N-type low voltage channel region, such that each of the depletion high voltage NMOS device and the depletion low voltage NMOS device is turned ON when a gate-source voltage thereof is zero voltage.

Abstract: The disclosed embodiments relate to an integrated circuit structure and methods of forming them in which photonic devices are formed on the back end of fabricating a CMOS semiconductor structure containing electronic devices. Doped regions associated with the photonic devices are formed using microwave annealing for dopant activation.

Abstract: A capacitor structure including a silicon material layer, a support frame layer, and a capacitor is provided. The support frame layer is disposed in the silicon material layer. The support frame layer has recesses. There is a cavity between two adjacent recesses. The support frame layer is located between the cavity and the recess. The support frame layer has a through hole directly above the cavity. The capacitor is disposed in the silicon material layer. The capacitor includes a first insulating layer and a first electrode layer. The first insulating layer is disposed on the support frame layer. The first electrode layer is disposed on the first insulating layer and fills the recess and the cavity.

Abstract: A process for preparing a thin layer made of ferroelectric material based on alkali metal, exhibiting a determined Curie temperature, transferred from a donor substrate to a carrier substrate by using a transfer technique including implanting light species into the donor substrate in order to produce an embrittlement plane, the thin layer having a first, free face and a second face that is arranged on the carrier substrate. The process comprises a first heat treatment of the transferred thin layer at a temperature higher than the Curie temperature, the thin layer exhibiting a multi-domain character upon completion of the first heat treatment, and introducing, after the first heat treatment, protons into the thin layer, followed by applying a second heat treatment of the thin layer at a temperature lower than the Curie temperature to generate an internal electric field that results in the thin layer being made single domain.

Abstract: A method of fabricating a transistor structure is provided. The method comprises forming a gate electrode in a dielectric layer of an interconnect structure; forming a monolayer on a portion of the dielectric layer laterally spaced from the gate electrode; sequentially forming a ferroelectric layer, a barrier layer and a channel layer on the gate electrode; and forming a source/drain electrode on the channel layer.

Abstract: A method of making a semiconductor die includes forming, over a substrate, a stack including insulating layers and sacrificial layers alternatively on top of each other; replacing a portion of first sacrificial layers located in a first portion of the stack to form first gate layers; forming first channel layers extending in a first direction in the first portion; forming first memory layers extending in the first direction in the first portion; replacing a portion of second sacrificial layers located in a second portion of the stack to form second gate layers; forming second channel layers extending in the first direction in the second portion; and forming second memory layers extending in the first direction in the second portion.

Abstract: A display panel and a method of manufacturing the display panel are provided. The display panel includes: a substrate including a transmission area, a display area surrounding the transmission area, and an intermediate area between the transmission area and the display area; a light emitting device; and a groove in the intermediate area and including a first opening of a metal layer including a first sublayer, a second sublayer, and a third sublayer sequentially stacked and a second opening of an inorganic layer covering the metal layer, wherein the first opening includes a first opening of the first sublayer, a second opening of the second sublayer, and a third opening of the third sublayer, which overlap each other, and an inner surface of the second sublayer includes a concave portion recessed in a direction farther away from a center of the first opening than an inner surface of the first sublayer and an inner surface of the third sublayer.

Abstract: A transparent display device includes a substrate in which a sub-pixel having an organic light emitting diode and an auxiliary sub-pixel adjacent to the sub-pixel and having an auxiliary organic light emitting diode are placed, wherein the organic light emitting diode includes a 1-1 electrode in which a transparent conductive layer and a reflective layer are laminated, and the auxiliary organic light emitting diode includes a 1-2 electrode in which the transparent conductive layer is extended and provided.