Patents Examined by Sheng-Jen Tsai
  • Patent number: 11113231
    Abstract: In a processing in memory (PIM) method using a memory device, m*n multiplicand arrangement bits are stored in m*n memory cells by copying and arranging m multiplicand bits of a multiplicand value and m*n multiplier arrangement bits are stored in m*n read-write unit circuits corresponding to the m*n memory cells by copying and arranging n multiplier bits of a multiplier value. The m*n multiplicand arrangement bits stored in the m*n memory cells are selectively read based on the m*n multiplier arrangement bits stored in the m*n read-write unit circuits, and m*n multiplication bits are stored in the m*n read-write unit circuits based on the selectively read m*n multiplicand arrangement bits. A multiplication value of the multiplicand value and the multiplier value is determined based on the m*n multiplication bits stored in the m*n read-write unit circuits.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Youngsun Song
  • Patent number: 11106374
    Abstract: A method is used in managing inline data de-duplication in storage systems. The method receives a request to write data at a logical address of a file in a file system of a storage system. The method determines whether the data can be de-duplicated to matching data residing on the storage system in a compressed format. Based on the determination, the method uses a block mapping pointer associated with the matching data to de-duplicate the data. The block mapping pointer includes a block mapping of a set of compressed data extents and information regarding location of the matching data within the set of compressed data extents.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: August 31, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, Christopher Seibel, Bruce Caram, Alexei Karaban
  • Patent number: 11106592
    Abstract: The present invention is directed to a system and method which employ two memory access paths: 1) a cache-access path in which block data is fetched from main memory for loading to a cache, and 2) a direct-access path in which individually-addressed data is fetched from main memory. The system may comprise one or more processor cores that utilize the cache-access path for accessing data. The system may further comprise at least one heterogeneous functional unit that is operable to utilize the direct-access path for accessing data. In certain embodiments, the one or more processor cores, cache, and the at least one heterogeneous functional unit may be included on a common semiconductor die (e.g., as part of an integrated circuit). Embodiments of the present invention enable improved system performance by selectively employing the cache-access path for certain instructions while selectively employing the direct-access path for other instructions.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Steven J. Wallach, Tony M. Brewer
  • Patent number: 11093393
    Abstract: A system and a method provide a memory-access technique that effectively parallelizes DRAM operations and coherency operations to reduce memory-access latency. The system may include a memory controller, an interconnect and a processor. The interconnect may be coupled to the memory controller. The processor may be coupled to the memory controller through a first path and a second path in which the first path is through the interconnect and the second path bypasses the interconnect. The processor may be configured to send substantially concurrently a memory access request to the memory controller via the first path and send a page activation request or a hint request to the memory controller via the second path so that the DRAM access operations appear to be masked, or hidden by the coherency operations.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: August 17, 2021
    Inventors: Hien Le, Junhee Yoo, Vikas Kumar Sinha, Robert Bell, Matthew Derrick Garrett
  • Patent number: 11093346
    Abstract: An apparatus for performing backup operations for data packets by a backup agent is provided. The apparatus predicts a first backup time period of completing a first backup operation for the data packets and determines a second backup time period of performing the first backup operation until the first backup operation is stopped at a point of time. The apparatus also identifies an incomplete status of the first backup operation at the point of time based on a comparison between the first backup time period and the second backup time period, and collects information describing the incomplete status. The apparatus further starts a second backup operation for the data packets from the incomplete status based on the information.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: August 17, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mahesh Reddy A. V., Swaroop Shankar DH, Mahantesh Ambaljeri, Chetan Battal
  • Patent number: 11093170
    Abstract: Techniques are provided for splitting a computer dataset between multiple storage locations based on a workload footprint analysis of that dataset. As a computer accesses data storage, its input/output (I/O) access can be monitored, as well as a working dataset of that dataset. The I/O access patterns can be used to determine an application of the computer that is generating the I/O. The application and the working dataset can be used to determine a split for the dataset across multiple storage locations. The dataset can then be split according to the determined split.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: August 17, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Alexey Fomin, Yuri Zagrebin, Nickolay Dalmatov
  • Patent number: 11086527
    Abstract: Systems and methods for pre-fetching data based on memory usage patterns. An example method comprises: receiving a first memory access request identifying a first memory block; receiving a second memory access request identifying a second memory block; update a memory access tracking data structure by incrementing a sequence counter corresponding to a memory access sequence that references the first memory block and the second memory block; receive a third memory access request identifying a third memory block; identifying, based on the memory access tracking data structure, a sequence counter having a maximal value among sequence counters associated with memory access sequences that reference the third memory block; and pre-fetching a fourth memory block corresponding to the identified sequence counter.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: August 10, 2021
    Assignee: Parallels International GmbH
    Inventors: Anton Zelenov, Nikolay Dobrovolskiy, Serguei M. Beloussov
  • Patent number: 11079951
    Abstract: Embodiments are disclosed for a multi-tier storage system (MTSS). The techniques include identifying a first data extent stored in a first storage pool of MTSS based on a read-write heat mapping by the MTSS. The first data extent is associated with a mirrored volume. The first data extent is a mirrored copy of a second data extent stored in a second storage pool of the MTSS. The first storage pool is asymmetric to the second storage pool. The techniques also include determining that a second top promotion tier of the second storage pool is faster than a first top promotion tier of the first storage pool. The techniques further include promoting the second data extent to the second top promotion tier based on the determination. Additionally, the techniques include updating an I/O access policy to direct future I/O operations for the mirrored volume to the second data extent.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: August 3, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kushal Patel, Mohit Chitlange, Sarvesh S. Patel, Ajinkya Nanavati
  • Patent number: 11074017
    Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage devices, for data processing. One of the methods includes maintaining, by a storage system, a plurality of storage devices that include at least a first tier storage device and a second tier storage device. The storage system receives a write request of a ledger data, determines whether a type of the ledger data is block data, and, in response to determining that the type of the ledger data is block data, writes the ledger data into the second tier storage device.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: July 27, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventor: Shikun Tian
  • Patent number: 11068349
    Abstract: Systems, methods, and computer program products are provided for reducing the size of image level backups. An example method receives backup parameters identifying a physical or Virtual Machine (VM) to backup and at least one file system object to include in the backup. The method connects to production storage corresponding to the selected physical or virtual machine and obtains access to data stored in disk corresponding to the selected file system object(s). The method fetches file allocation table (FAT) blocks from the disk and parses contents of the FAT blocks to determine if the disk blocks correspond to the selected file system object(s). The method creates a backup disk image FAT comprising blocks corresponding to the selected file system object(s), The method creates a reconstructed disk image FAT blocks corresponding to the backup FAT and disk image data blocks belonging to the selected file system object(s) and all other disk image data blocks are saved as zero blocks.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: July 20, 2021
    Assignee: Veeam Software AG
    Inventors: Ratmir Timashev, Anton Gostev
  • Patent number: 11068183
    Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shekoufeh Qawami, Rajesh Sundaram
  • Patent number: 11061575
    Abstract: Read-only or pseudo table of contents (TOC) register. A value for a register to be used to access a reference data structure for a given module is obtained. The register is a virtual register that provides the value for the given module absent backing the register in memory. The value is used to access the reference data structure to obtain a variable address to be used by the given module.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: July 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 11061576
    Abstract: Read-only or pseudo table of contents (TOC) register. A value for a register to be used to access a reference data structure for a given module is obtained. The register is a virtual register that provides the value for the given module absent backing the register in memory. The value is used to access the reference data structure to obtain a variable address to be used by the given module.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: July 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 11048627
    Abstract: Provided are a computer program product, system, and method for determining the location for volumes of data being initially stored within a storage space, regardless of the physical location of the data. The storage space includes stripes composed of volumes, which can be logically represented as a utilization histogram of stripe locations offset from one another. Sometime the stripes are fully allocated with one large volume or partially allocated with multiple, arbitrary-sized smaller volumes. When there are multiple smaller volumes that do not utilize all of the available stripe space, gaps form. To minimize the creation of such gaps, when a volume of data is initially stored, a start location to place the volume of data is selected by using selection criteria as guidance.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventor: Michael Keller
  • Patent number: 11042331
    Abstract: According to one embodiment, a memory device includes a first memory, a control circuit controlling the first memory, and a second memory storing a second program. The second program manages management information associated with the first memory, sends the management information conforming to a specific interface to a first program if a command conforming to the specific interface is an output command to output the management information. The second program receives first information conforming to the specific interface and issued by the first program, translates the first information into second information corresponding to the second program, translates the second information into third information corresponding to the control circuit, and executes processing for the first memory in accordance with the third information.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 22, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Kanno, Hiroshi Nishimura, Hideki Yoshida
  • Patent number: 10997083
    Abstract: Address translation circuitry performs virtual-to-physical address translations using a page table hierarchy of page table entries, wherein a translation between a virtual address and a physical address is defined in a last level page table entry of the page table hierarchy. The address translation circuitry is responsive to receipt of the virtual address to perform a translation determination with reference to the page table hierarchy, wherein an intermediate level page table entry of the page table hierarchy stores an intermediate level pointer to the last level page table entry.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: May 4, 2021
    Assignee: ARM Limited
    Inventors: Geoffrey Wyman Blake, Prakash S. Ramrakhyani, Andreas Lars Sandberg
  • Patent number: 10996878
    Abstract: Scalable architectures provide resiliency and redundancy and are suitable for cloud deployment. The architectures support extreme data throughput requirements. In one implementation, the architectures provide a serving layer and an extremely high speed processing lane. With these and other features, the architectures support complex analytics, visualization, rule engines, and centralized pipeline configuration.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: May 4, 2021
    Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITED
    Inventors: Jagaran Das, Teresa Sheausan Tung, Srinivas Yelisetty, Daniel Corin
  • Patent number: 10969994
    Abstract: A memory system having memory components and a processing device to: receive, from a host system, write commands to store data in the memory components; store the write commands in a buffer; execute at least a portion of the write commands; determine an amount of available capacity of the buffer that becomes available after execution of at least the portion of the write commands; receive, from the host system, a request for information about available capacity of the buffer; and determine whether to transmit a response signal corresponding to the request based at least in part on the amount of available capacity.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: April 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dhawal Bavishi, Trevor Conrad Meyerowitz
  • Patent number: 10936199
    Abstract: A method of a flash controller to be coupled between a flash memory device and a host device is provided. The flash memory device has a plurality of blocks each having a plurality of pages, and the method comprises: receiving a trim/erase/unmap command from the host device; obtaining a storage space, which is to be erased, from the trim/erase/unmap command; comparing a space size of the storage space with a threshold to determine whether the space size is larger than the threshold; and resetting valid page counts of the plurality of blocks of the flash memory device when the space size is larger than the threshold.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: March 2, 2021
    Assignee: Silicon Motion, Inc.
    Inventor: Hsu-Ping Ou
  • Patent number: 10929048
    Abstract: Dynamically generating proxy virtual machines (VMs) in a virtual center (vCenter) serving a backup server, by deploying a source proxy VM by passing network data to the vCenter, passing a set of internet protocol (IP) addresses and network configuration information to the vCenter to be used by the dynamically generated proxy VMs, receiving an indication from the backup server that new proxy VMs are required, and performing, in the vCenter, an instant clone operation to spawn one or more new proxy VMs. The method may further comprise passing the IP address and network configuration information for the new proxy VMs to the backup server for registration within the backup server, and using the new proxy VMs for backup operations of the backup server.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: February 23, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Sharath Talkad Srinivasan, Shahid Paloth Parambil, Rakesh Kumar