Patents Examined by Sheng-Jen Tsai
  • Patent number: 9411574
    Abstract: Embodiments of a system and method to update firmware across multiple devices in a process facility using a single domain of a FOUNDATION Fieldbus protocol. In one embodiment, the system has a receiving device that couples with a pair of target devices, e.g., a first target device and a second target device. The receiving device includes operating instructions that can process an input and generate an output. The input comprises data comprising a first firmware component and a second firmware component for, respectively, the first target device and the second target device. The receiving device can direct the firmware component to the appropriate target device; generating a first output and a second output that distribute the firmware components to complete the upgrade process.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: August 9, 2016
    Assignee: Dresser, Inc.
    Inventors: Vladimir Dimitrov Kostadinov, Larry Gene Schoonover, Anatoly Podpaly
  • Patent number: 9405621
    Abstract: A controller for a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD) increases flash endurance using a DRAM buffer. Host accesses to flash are intercepted by the controller and categorized as data types of paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type in the DRAM before storage by lower-level flash devices such as eMMC, UFS, or iSSD. Caches in the DRAM buffer for storing each data type are managed and flushed to the flash devices by the controller. Write dates are stored for pages or blocks for management functions. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: August 2, 2016
    Assignee: Super Talent Technology, Corp.
    Inventors: Frank Yu, Abraham C. Ma, Shimon Chen
  • Patent number: 9400799
    Abstract: Techniques and mechanisms are provided for migrating data blocks around a cluster during node addition and node deletion. Migration requires no downtime, as a newly added node is immediately operational while the data blocks are being moved. Blockmap files and deduplication dictionaries need not be updated.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: July 26, 2016
    Assignee: Dell Products L.P.
    Inventors: Vinod Jayaraman, Abhijit Dinkar, Mark Taylor, Goutham Rao, Michael E. Root, Murali Bashyam
  • Patent number: 9396464
    Abstract: A method of updating multi-media content at a digital download kiosk is described. The method comprises receiving a secure portable storage device into a portable device reader/writer in the kiosk; reading the secure portable storage device to ascertain if authorized multi-media content is stored thereon; uploading the multi-media content from the secure portable storage device to a data store accessible by the kiosk; and indicating when the multi-media content has been uploaded. The portable storage device may have been received by mail from a supplier, and the method may further comprise removing the portable storage device from the portable storage device reader/writer, and returning the removed portable storage device to the supplier by mail.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: July 19, 2016
    Assignee: NCR Corporation
    Inventor: James Henderson
  • Patent number: 9384023
    Abstract: A method for enabling inter-process communication between a first application and a second application, the first application running within a first context and the second application running within a second context of a virtualization system is described. The method includes receiving a request to attach a shared region of memory to a memory allocation, identifying a list of one or more physical memory pages defining the shared region that corresponds to the handle, and mapping guest memory pages corresponding to the allocation to the physical memory pages. The request is received by a framework from the second application and includes a handle that uniquely identifies the shared region of memory as well as an identification of at least one guest memory page corresponding to the memory allocation. The framework is a component of a virtualization software, which executes in a context distinct from the context of the first application.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: July 5, 2016
    Assignee: VMware, Inc.
    Inventors: Gustav Seth Wibling, Jagannath Gopal Krishnan
  • Patent number: 9383928
    Abstract: A CAS data storage system with one or more source CAS data storage spaces and one or more destination CAS data storage spaces, and a communication line therebetween, receives input data at the source storage space for local storage and for replication to the destination CAS storage space. CAS metadata is used in the replication procedure between the two separate CAS storage spaces. Thus, data at the source storage space is used to form an active buffer for transfer to the destination storage space, the active buffer holding a hash result of the respective data item and a storage address. The system detects whenever there is more than one data item in said active buffer sharing a same storage address and upon such detection transfers a respective hash result of only the last of the data items.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: July 5, 2016
    Assignee: EMC CORPORATION
    Inventors: Erez Webman, Ehud Rokach, Shahar Frank
  • Patent number: 9367247
    Abstract: Incoming memory access requests are routed in a set of incoming queues, the incoming memory access requests comprise a range of host logical block addresses (LBAs) that correspond to a memory space of a primary memory. The host LBA range is directly mapped to clusters of secondary memory, the secondary memory corresponding to a memory space of a secondary memory. Each incoming memory access request queued in the set of incoming queues is transformed into one or more outgoing memory access requests that include a range of secondary memory clusters or one or more clusters of secondary memory clusters. The outgoing memory access requests are routed in a set of outgoing queues. The secondary memory is accessed using the outgoing memory access requests.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: June 14, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventor: Sumanth Jannyavula Venkata
  • Patent number: 9355689
    Abstract: Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: May 31, 2016
    Assignee: Oracle International Corporation
    Inventors: David Jeffrey, Clement Fang, Neil Duncan, Heechoul Park, Lik Cheng, Gregory F. Grohoski
  • Patent number: 9355109
    Abstract: A method for maintaining an index in multi-tier data structure includes providing a plurality of a storage devices forming the multi-tier data structure, caching an index of key-value pairs across the multi-tier data structure, wherein each of the key-value pairs includes a key, and one of a data value and a data pointer, the key-value pairs stored in the multi-tier data structure, providing a journal for interfacing with the multi-tier data structure, providing a plurality of zone allocators recording which zones of the multi-tier data structure are in used, and providing a plurality of zone managers for controlling access to cache lines of the multi-tier data structure through the journal and zone allocators, wherein each zone manager maintains a header object pointing to data to be stored in an allocated zone.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: May 31, 2016
    Assignee: The Research Foundation For the State University of New York
    Inventors: Shrikar Archak, Sagar Dixit, Richard P. Spillane, Erez Zadok
  • Patent number: 9330009
    Abstract: A method and system for use in managing data storage is disclosed. Data storage in a data storage system is managed. The data storage system comprises a first data storage tier and a second data storage tier configured such that the performance characteristics associated with one of the data storage tiers is superior to the other data storage tier. I/O activity is determined in connection with a data group stored on one of the first and second data storage tiers. It is determined whether to migrate the data group stored on the one of the first and second data storage tiers to the other data storage tier based on the performance characteristics associated with the other data storage tier and the determined I/O activity. The data group is migrated to the other data storage tier in response to determining to migrate the data group to the other data storage tier.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: May 3, 2016
    Assignee: EMC Corporation
    Inventors: Dean D. Throop, Dennis T. Duprey, Miles de Forest, Michael D. Haynes
  • Patent number: 9330432
    Abstract: Techniques are disclosed relating to arbitration of requests to access a register file. In one embodiment, an apparatus includes a write queue and a register file that includes multiple entries. In one embodiment, the apparatus is configured to select a request from a plurality of requests based on a plurality of request characteristics, and write data from the accepted request into a write queue. In one embodiment, the request characteristics include: whether a request is a last request from an agent for a given register file entry and whether the request finishes a previous request. In one embodiment, a final arbiter is configured to select among requests from the write queue, a read queue, and multiple execution pipelines to access banks of the register file in a given cycle.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: May 3, 2016
    Assignee: Apple Inc.
    Inventors: Andrew M. Havlir, Sreevathsa Ramachandra, William V. Miller
  • Patent number: 9323586
    Abstract: We teach a powerful approach that greatly simplifies the design of non-blocking mechanisms and data structures, in part by, largely separate the issues of correctness and progress. At a high level, our methodology includes designing an “obstruction-free” implementation of the desired mechanism or data structure, which may then be combined with a contention management mechanism whose role is to facilitate the conditions under which progress of the obstruction-free implementation is assured. In general, the contention management mechanism is separable semantically from an obstruction-free concurrent shared/sharable object implementation to which it is/may be applied. In some cases, the contention management mechanism may actually be coded separately from the obstruction-free implementation. We elaborate herein on the notions of obstruction-freedom and contention management, and various possibilities for combining the two.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: April 26, 2016
    Assignee: Oracle International Corporation
    Inventors: Mark S. Moir, Victor M. Luchangco, Maurice Herlihy
  • Patent number: 9323655
    Abstract: Managing data in a storage system having a plurality of classes of storage includes determining an amount of data to be provided on at least one of the classes of storage according to a policy, dynamically setting a threshold according to the amount of data to be provided on the at least one of the classes or an expected performance based on the threshold, and placing data on particular classes of storage based on the threshold. Dynamically setting a threshold may include sorting data portions according to at least one score thereof and may include determining a particular score corresponding to the amount of data to be provided. The data portions may be provided in a histogram having a horizontal scale corresponding to a score value and a vertical scale corresponding to a number of data portions having a particular value.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 26, 2016
    Assignee: EMC Corporation
    Inventors: Adnan Sahin, Alexandr Veprinsky, Marik Marshak, Hui Wang, Xiaomei Liu, Owen Martin, Sean C. Dolan
  • Patent number: 9317222
    Abstract: A centralized content addressed storage (CAS) application and a method for providing data protection are implemented by running a CAS application on a virtualization layer of a computer platform. The virtualization layer presents to the CAS application a normalized representation of a hardware subsystem of the computer platform, shielding the CAS application from actual hardware devices of the computer platform. A storage device of the computer platform is used to store a raw data set and the CAS application generates a backup data set of the raw data set. The CAS application stores the backup data set to an archive mechanism of the computer platform and can also restore and recover the raw data set in the event it is lost, corrupted or otherwise destroyed. Multiple CAS applications can be operated separately or together and they may be the same or differ.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: April 19, 2016
    Assignee: EMC CORPORATION
    Inventor: Jedidiah Yueh
  • Patent number: 9313143
    Abstract: In accordance with some aspects of the present invention, systems and methods are provided for dynamically and/or automatically selecting and/or modifying data path definitions that are used in performing storage operations on data. Alternate data paths may be specified or selected that use some or all resources that communicate with a particular destination to improve system reliability and performance. The system may also dynamically monitor and choose data path definitions to optimize system performance, conserve storage media and promote balanced load distribution.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: April 12, 2016
    Assignee: Commvault Systems, Inc.
    Inventors: Rajiv Kottomtharayil, Parag Gokhale, Marcus S. Muller
  • Patent number: 9298609
    Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: March 29, 2016
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern
  • Patent number: 9274592
    Abstract: A technique to retain cached information during a low power mode, according to at least one embodiment. In one embodiment, information stored in a processor's local cache is saved to a shared cache before the processor is placed into a low power mode, such that other processors may access information from the shared cache instead of causing the low power mode processor to return from the low power mode to service an access to its local cache.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: March 1, 2016
    Assignee: Intel Corporation
    Inventors: Sanjeev Jahagirdar, Varghese George, Jose Allarey
  • Patent number: 9264380
    Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
    Type: Grant
    Filed: May 7, 2011
    Date of Patent: February 16, 2016
    Assignee: Broadcom Corporation
    Inventor: David T. Hass
  • Patent number: 9250820
    Abstract: A system and method for storing infrequently accessed data with reduced power consumption. In one embodiment, a solid state drive (SSD) includes flash memory and environmental data logging circuitry. The SSD is shut off or operated in a sleep mode to reduce power consumption, and turned on or transitioned to an active mode as needed when data on the SSD is to be accessed, or when a calculation, based on a number of erase cycles previously performed in the flash memory and on a temperature history of the SSD indicates that a data refresh may be needed to prevent data corruption in the SSD, due to data retention limitation of the nonvolatile memory in the SSD.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 2, 2016
    Assignee: NXGN Data, Inc.
    Inventors: Nader Salessi, Joao Alcantara
  • Patent number: 9251149
    Abstract: Specified data sets may be tracked from creation to end-of-life (e.g., deletion). Between creation and end-of-life, data set storage changes may be recorded (i.e., when additional storage is allocated or when some storage is released). During a subsequent allocation cycle, this information may be used in conjunction with user-specified allocation rules to manage or control the data set's initial allocation.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: February 2, 2016
    Assignee: BMC SOFTWARE, INC.
    Inventors: Marek Szowa, Kerry Zack