Patents Examined by Shouxiang Hu
  • Patent number: 12040218
    Abstract: A method of forming semiconductor device, including forming a first protective strip and a second protective strip on a semiconductor substrate. The first protective strip and the second protective strip extend in a first direction and are alternately arranged in a second direction perpendicular to the first direction. The first protective strip and the second protective strip are spaced apart from each other. The first protective strip is cut by selectively removing a portion of the first protective strip. The second protective strip is cut by selectively removing a portion of the second protective strip. The semiconductor substrate is etched to form an isolation trench. Remaining portions of the first and second protective strips are removed. An isolation feature is filled into the isolation trench. The isolation feature defines a plurality of strip-shaped active regions. Capacitor contacts are formed on both ends of each of the strip-shaped active regions.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: July 16, 2024
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Frederick Chen
  • Patent number: 12033887
    Abstract: A multi-color display includes a backplane having backplane circuitry, an array of micro-LEDs electrically integrated with backplane circuitry of the backplane, a color conversion layer over each of a plurality of light emitting diodes, and a plurality of isolation walls separating adjacent micro-LEDs of the array.
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: July 9, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Daihua Zhang, Yingdong Luo, Mingwei Zhu, Hou T. Ng, Sivapackia Ganapathiappan, Nag B. Patibandla
  • Patent number: 12027447
    Abstract: A semiconductor device includes a first conductive element electrically connected to an interconnect structure, wherein the first conductive element includes a first conductive material. The semiconductor device further includes an RDL over the first conductive element and electrically connected to the first conductive element, wherein the RDL includes a second conductive material different from the first conductive material. The semiconductor device further includes a passivation layer over the RDL, wherein a top portion of a sidewall of the second passivation layer includes a convex curve protruding in a direction parallel to a top surface of the interconnect structure, a width of the top portion at a bottom of the convex curve is less than a width of the top portion at a middle of the convex curve, and the middle of the convex curve is above the bottom of the convex curve.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Anhao Cheng, Chun-Chang Liu
  • Patent number: 12027491
    Abstract: A multi-chip package comprising: an interconnection substrate comprising an interconnection bridge embedded in the interconnection substrate, and an interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection layer and the interconnection bridge, and a polymer layer between the first and second interconnection metal layers, wherein the interconnection bridge is embedded in the interconnection scheme and has sidewalls surrounded by the polymer layer; a semiconductor IC chip over the interconnection substrate and across over an edge of the interconnection bridge; a memory chip over the interconnection substrate and across over an edge of the interconnection bridge, wherein the interconnection bridge comprises a plurality of metal interconnects configured for a data bus coupling the semiconductor IC chip to the memory chip, wherein a bitwidth of the data bus between the semiconductor IC chip and the memory chip is greater than or equa
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: July 2, 2024
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 12027369
    Abstract: The present application relates to a mask structure, a semiconductor structure and methods for manufacturing the same. The method for manufacturing a mask structure includes: dividing an overall structure into two regions, and developing the array region and the periphery region with a negative photoresist.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: July 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Qiang Wan, Jun Xia, Kangshu Zhan, Sen Li, Penghui Xu, Tao Liu
  • Patent number: 12021138
    Abstract: A power control switch assembly. The assembly may include a thyristor device, where the thyristor device includes a first device terminal, a second device terminal, and a gate terminal> The assembly may include a negative temperature coefficient (NTC) device, electrically coupled to the gate terminal of the thyristor device on a first end, and electrically coupled to the first device terminal of the thyristor device on a second end, wherein the NTC device is thermally coupled to the thyristor device.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: June 25, 2024
    Assignee: Littelfuse, Inc.
    Inventor: Koichiro Yoshimoto
  • Patent number: 12022648
    Abstract: The present disclosure provides a semiconductor structure having an air gap surrounding a lower portion of a bit line, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate; a bit line structure disposed over the substrate; a first dielectric layer, surrounding the bit line structure; a second dielectric layer, surrounding a lower portion of the first dielectric layer, wherein the second dielectric layer is separated from the first dielectric layer by a first air gap; and a third dielectric layer, surrounding an upper portion of the first dielectric layer and sealing the first air gap.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: June 25, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Ching-Kai Chuang
  • Patent number: 11984316
    Abstract: A device includes a substrate; a first layer over the substrate, the first layer containing a plurality of fin features and a trench between two adjacent fin features. The device also includes a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.
    Type: Grant
    Filed: May 22, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Jiun Lin, Ching-Yu Chang, Hai-Ching Chen, Tien-I Bao
  • Patent number: 11984360
    Abstract: A circuit includes at least one bipolar transistor and at least one variable capacitance diode. The circuit is fabricated using a method whereby the bipolar transistor and variable capacitance diode are jointly produced on a common substrate.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: May 14, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Gregory Avenier, Alexis Gauthier, Pascal Chevalier
  • Patent number: 11978787
    Abstract: A power control switch assembly. The assembly may include a thyristor device, where the thyristor device includes a first device terminal, a second device terminal, and a gate terminal> The assembly may include a negative temperature coefficient (NTC) device, electrically coupled to the gate terminal of the thyristor device on a first end, and electrically coupled to the first device terminal of the thyristor device on a second end, wherein the NTC device is thermally coupled to the thyristor device.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: May 7, 2024
    Assignee: Littelfuse, Inc.
    Inventor: Koichiro Yoshimoto
  • Patent number: 11974426
    Abstract: A semiconductor device includes a substrate, a bit line conductive layer disposed on the substrate and extending in a first lateral direction substantially parallel to a surface of the substrate, first and second channel structures disposed on the bit line conductive layer to be spaced apart from each other in the first lateral direction, first and second gate dielectric layers disposed on side surfaces of the first and second channel structures over the substrate, first and second gate line conductive layers disposed on the first and second gate dielectric layers, respectively, the first and second gate line conductive layers common to the first and second channel structures, respectively, and extending in a second lateral direction perpendicular to the first lateral direction and substantially parallel to the surface of the substrate, and first and second storage node electrode layers disposed over the first and second channel structures, respectively.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: April 30, 2024
    Assignee: SK hynix Inc.
    Inventors: Jae Hyun Han, Dong Ik Suh, Jae Gil Lee
  • Patent number: 11968824
    Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: April 23, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngjun Kim, Seokhyun Kim, Jinhyung Park, Hoju Song, Hyeran Lee, Sungwoo Kim, Bongsoo Kim
  • Patent number: 11961836
    Abstract: An integrated circuit structure comprises one or more fins extending above a surface of a substrate over an N-type well. A gate is over and in contact with the one or more fins. A second shallow N-type doping is below the gate and above the N-type well.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 16, 2024
    Assignee: Intel Corporation
    Inventors: Hyung-Jin Lee, Mark Armstrong, Saurabh Morarka, Carlos Nieva-Lozano, Ayan Kar
  • Patent number: 11955481
    Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: April 9, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Jean Jimenez Martinez
  • Patent number: 11956946
    Abstract: The semiconductor structure manufacturing method includes the steps of: providing a substrate with bit line contact regions and isolation regions located between adjacent bit line contact regions; forming a groove in the substrate, the bottom of the groove exposes the bit line contact region and the isolation region adjacent to the bit line contact region; forming a contact region isolation layer covering at least sidewalls of the groove; and forming a contact region to cover the contact region isolating the surface of the layer and filling the bit line contact layer of the groove, the bit line contact layer being in contact with the bit line contact region at the bottom of the groove; forming a bit line layer on the bit line contact layer. The invention avoids damage to the sidewalls of the active region in the substrate.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: April 9, 2024
    Assignee: ChangXin Memory Technologies, Inc.
    Inventors: Yexiao Yu, Zhongming Liu, Longyang Chen, Jia Fang
  • Patent number: 11956968
    Abstract: Provided are a memory device and a method of forming the same. The memory device includes a first tier on a substrate and a second tier on the first tier. The first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-I Wu, Yu-Ming Lin, Sai-Hooi Yeong, Han-Jong Chia
  • Patent number: 11935789
    Abstract: A microelectronic device has a substrate attached to a substrate pad on a first face of the substrate, and a component attached to the substrate on the first face. The substrate has a component placement guide on the first face. The substrate has a singulation guide on a second face of the substrate, located opposite from the first face. The microelectronic device is formed by attaching the component to a substrate sheet which contains the substrate. The substrate sheet with the component is mounted on a singulation film so that the component contacts the singulation film. The singulation guide on the second face of the substrate is located opposite from the singulation film. The substrate is singulated from the substrate sheet. The substrate with the component is attached to the substrate pad on the first face of the substrate, adjacent to the component.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: March 19, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chang-Yen Ko, J K Ho
  • Patent number: 11929423
    Abstract: A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: March 12, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sebastian Meier, Helmut Rinck, Mike Mittelstaedt
  • Patent number: 11929259
    Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: March 12, 2024
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Ian Harvey Arellano, Aaron Cadag, Ela Mia Cadag
  • Patent number: 11929425
    Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Chung Wang, Chao-Ching Cheng, Tzu-Chiang Chen, Tung Ying Lee