Patents Examined by Shouxiang Hu
  • Patent number: 10971476
    Abstract: A bottom package substrate is provided that includes a plurality of metal posts that electrically couple through a die-side redistribution layer to a plurality of die interconnects. The metal posts and the die interconnects are plated onto a seed layer on the bottom package substrate.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: April 6, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Ratibor Radojcic, Dong Wook Kim
  • Patent number: 10964585
    Abstract: Disclosed are a semiconductor structure and a method for forming same.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: March 30, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventors: Zhang Tianhao, Wu Yichao
  • Patent number: 10964593
    Abstract: A semiconductor structure and a method for forming the same are provided.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: March 30, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Jin Jisong
  • Patent number: 10950778
    Abstract: Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: March 16, 2021
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Aurelius L. Graninger, Joel D. Strand, Micah John Atman Stoutimore, Zachary Kyle Keane, Jeffrey David Hartman, Justin C. Hackley
  • Patent number: 10950641
    Abstract: An image sensor includes a semiconductor substrate including a plurality of photo-sensing devices, a photoelectric conversion device disposed on the semiconductor substrate and absorbing the mixed light of a first color and a second color, and a color filter disposed on one side of the photoelectric conversion device and configured to selectively transmit a mixed light including a third color, and an electronic device including the image sensor is provided.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong Wan Jin, Gae Hwang Lee, Seon-Jeong Lim, Sung Young Yun, Kwang Hee Lee
  • Patent number: 10943868
    Abstract: A semiconductor structure includes a first low-k dielectric layer disposed over a semiconductor substrate, a first conductive feature and a second conductive feature disposed in the first low-k dielectric layer, a second low-k dielectric layer disposed in the first low-k dielectric layer and interposed between the first conductive feature and the second conductive feature, where the second low-k dielectric layer includes an air gap, and an etch-stop layer disposed at an interface between the first low-k dielectric layer and the second low-k dielectric layer. The first low-k dielectric layer includes carbon whose concentration is graded in a direction away from the etch-stop layer.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Hsiang-Wei Lin
  • Patent number: 10943843
    Abstract: A semiconductor package structure includes a conductive trace layer, a semiconductor die over the conductive trace layer, a structure enhancement layer surrounding the semiconductor die, and an encapsulant covering the semiconductor die and the structure enhancement layer. The structure enhancement layer coincides with a mass center plane of the semiconductor package structure. The mass center plane is parallel to a top surface of the semiconductor die. A method for manufacturing the semiconductor package structure is also provided.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: March 9, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsiu-Chi Liu, Hsu-Nan Fang
  • Patent number: 10937762
    Abstract: A multi-chip package comprising: an interconnection substrate comprising an interconnection bridge embedded in the interconnection substrate, and an interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection layer and the interconnection bridge, and a polymer layer between the first and second interconnection metal layers, wherein the interconnection bridge is embedded in the interconnection scheme and has sidewalls surrounded by the polymer layer; a semiconductor IC chip over the interconnection substrate and across over an edge of the interconnection bridge; a memory chip over the interconnection substrate and across over an edge of the interconnection bridge, wherein the interconnection bridge comprises a plurality of metal interconnects configured for a data bus coupling the semiconductor IC chip to the memory chip, wherein a bitwidth of the data bus between the semiconductor IC chip and the memory chip is greater than or equa
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: March 2, 2021
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 10930498
    Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Chung Wang, Chao-Ching Cheng, Tzu-Chiang Chen, Tung Ying Lee
  • Patent number: 10923577
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cavity structures under shallow trench isolation regions and methods of manufacture. The structure includes: one or more cavity structures provided in a substrate material and sealed with an epitaxial material; and a shallow trench isolation region directly above the one or more cavity structures in the substrate material.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: February 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Johnatan A. Kantarovsky, Siva P. Adusumilli, Vibhor Jain
  • Patent number: 10916479
    Abstract: Semiconductor device and fabrication method are provided. The method includes: providing a semiconductor substrate; forming initial fins on the semiconductor substrate; forming a gate structure material layer on the semiconductor substrate and the initial fins, the gate material layer having a top surface higher than the initial fins; forming a trench in the gate structure material layer and the initial fins, which passes through the initial fins along a direction perpendicular to an extending direction of initial fins and in parallel with a surface of the semiconductor substrate to form initial fins into fins; forming an isolation layer in the trench having a top surface higher than the fins; and forming gate structures on both sides of the isolation layer by etching the gate structure material layer.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: February 9, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 10916578
    Abstract: A semiconductor apparatus in which are bonded a semiconductor substrate, in which a semiconductor element is arranged, and a supporting substrate is provided. A bonding layer for bonding the semiconductor substrate and the supporting substrate is arranged between the supporting substrate and a front side of the semiconductor substrate on the side of the supporting substrate. The bonding layer includes a first resin member arranged in a first region inside of an outer edge of the semiconductor substrate in an orthographic projection to the front side, and a second resin member arranged in a second region between the outer edge of the semiconductor substrate and the first region, in the orthographic projection to the front side. A linear expansion coefficient of the first resin member is less than a linear expansion coefficient of the second resin member.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: February 9, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takahiro Hachisu
  • Patent number: 10896954
    Abstract: An electronic device can include a semiconductor layer having a primary surface, a drift region adjacent to the primary surface, a drain region adjacent to the drift region and extending deeper into the semiconductor layer as compared to the drift region, a resurf region spaced apart from the primary surface, an insulating layer overlying the drain region, and a contact extending through the insulating layer to the drain region. In an embodiment, the drain region can include a sinker region that allows a bulk breakdown to the resurf region to occur during an overvoltage event where the bulk breakdown occurs outside of the drift region, and in a particular embodiment, away from a shallow trench isolation structure or other sensitive structure.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: January 19, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Moshe Agam, Ladislav {hacek over (S)}eliga, Thierry Coffi Herve Yao, Jaroslav Pjen{hacek over (c)}ák, Gary H. Loechelt
  • Patent number: 10886130
    Abstract: Some embodiments include a method of forming crystalline semiconductor material. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The deposition is conducted at a temperature of less than or equal to 500° C. Some embodiments include a method of forming a transistor. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The semiconductor material includes germanium. The crystalline semiconductor structures are doped to form a configuration having a first portion over a second portion. Insulative material is formed adjacent the second portion. A transistor gate is formed along the insulative material.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Manuj Nahar, Darwin Franseda Fan, Junting Liu-Norrod, Michael Mutch
  • Patent number: 10886145
    Abstract: A method of producing a surface-mountable multi-chip component includes providing a chip arrangement including a metallic conductor structure exposed at a rear side, a plurality of semiconductor chips and an housing material; and forming a solder stop coating on a rear side of the chip arrangement, wherein the solder stop coating separates connection regions of the conductor structure.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: January 5, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Michael Zitzlsperger, Tobias Gebuhr, Stephan Eicher
  • Patent number: 10879078
    Abstract: A method of patterning a resist layer is provided. The method includes forming the resist layer over the top surface of a silicon-containing layer that has a first contact angle. The method also includes exposing and developing the resist layer to form a patterned resist layer and expose a portion of the top surface of the silicon-containing layer. The method also includes applying a treating compound to the exposed portion of the top surface of the silicon-containing layer, so that the exposed portion of the top surface has a second contact angle that is greater than the first contact angle. The method also includes reflowing the patterned resist layer over the top surface of the silicon-containing layer having the second contact angle.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Wei Wang, Li-Po Yang, Ching-Yu Chang
  • Patent number: 10867922
    Abstract: A device includes a substrate; a first layer over the substrate, the first layer containing a metallic material, wherein the first layer includes a trench; and a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Jiun Lin, Ching-Yu Chang, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10867860
    Abstract: A method includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a gate spacer along a sidewall of the gate structure, where an upper surfaces of the gate structure is exposed by the gate spacer; depositing a gate film over the gate structure, the gate spacer, and the fin; performing one or more etching processes after depositing the gate film, where the one or more etching processes remove a first portion of the gate film from an upper surface of the fin and form a recess in the fin, where a second portion of the gate film remains on a sidewall of the gate spacer after the one or more etching processes; and forming an epitaxial source/drain region in the recess.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko
  • Patent number: 10859920
    Abstract: A fabrication method of a mask and a mask, a display panel and a touch panel are provided. The fabrication method of the mask includes: providing a substrate; forming a photoresist material layer on the substrate; and performing at least two scanning exposure processes on the photoresist material layer by using a scanning beam, wherein, each of the at least two scanning exposure processes is performed along a first direction parallel to a surface where the substrate is located, the scanning beam in each of the at least two scanning exposure processes scans the photoresist material layer in a scanning region having a preset width, at least one pair of adjacent scanning regions partially overlap with each other, and a partially overlapping region of the at least one pair of adjacent scanning regions is located in a first region of the mask.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: December 8, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Liqing Liao, Hongmin Li, Jian Tao
  • Patent number: 10861753
    Abstract: A method includes forming a gate stack over a semiconductor substrate, forming a first spacer layer on a sidewall of the gate stack, forming a sacrificial spacer film over the first spacer layer, forming an epitaxy structure on the semiconductor substrate, and performing an etching process on the sacrificial spacer film to form a gap between the first spacer layer and the epitaxy structure. An outer portion of the sacrificial spacer film has a topmost end higher than that of an inner portion of the sacrificial spacer film after performing the etching process. The method further includes forming a second spacer layer to seal the gap between the epitaxy structure and the first spacer layer.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Yu Lai, Kai-Hsuan Lee, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen