Patents Examined by Shouxiang Hu
  • Patent number: 10600829
    Abstract: The present disclosure provides a package base core and a sensor package structure. The package base core includes a substrate and at least one stopper, or the package base core includes a substrate, at least one stopper, and a compound. The sensor package structure includes a substrate, a first stopper, a second stopper, a sensing member, a first compound, a second compound, and a translucent member. The stopper (or the first and second stoppers) of the present disclosure is provided to form with a protruding portion on the substrate, so that an overflowing of the compound can be avoided, thereby increasing the reliability of the package base core.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: March 24, 2020
    Assignee: KINGPAK TECHNOLOGY INC.
    Inventors: Chung-Hsin Hsin, Chen-Pin Peng, Chien-Heng Lin, Kun-Chih Hsieh
  • Patent number: 10600783
    Abstract: A plurality of mandrels is formed on a silicon substrate. The mandrels are spaced apart at a given pitch, wherein at least one of the plurality of mandrels is formed having a first width, and at least another one of the plurality of mandrels is formed having a second width, and wherein the first width is greater than the second width. At least one structure is formed by removing at least a portion of the plurality of mandrels in a sidewall image transfer process without using a cut mask.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10600695
    Abstract: Techniques for forming VTFET devices with tensile- and compressively-strained channels using dummy stressor materials are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming bottom source and drains at a base of the fins; forming bottom spacers on the bottom source and drains; growing at least one dummy stressor material along sidewalls of the fins above the bottom spacers configured to induce strain in the fins; surrounding the fins with a rigid fill material; removing the at least one dummy stressor material to form gate trenches in the rigid fill material while maintaining the strain in the fins by the rigid fill material; forming replacement gate stacks in the gate trenches; forming top spacers on the replacement gate stacks; and forming top source and drains over the top spacers at tops of the fins. A VTFET device is also provided.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Kangguo Cheng, Shogo Mochizuki, Juntao Li
  • Patent number: 10593590
    Abstract: A method for the production of layers of solid material is contemplated. The method may include the steps of providing a solid body for the separation of at least one layer of solid material, generating defects by means of at least one radiation source, in particular a laser, in the inner structure of the solid body in order to determine a detachment plane along which the layer of solid material is separated from the solid body, and applying heat to a polymer layer disposed on the solid body in order to generate, in particular mechanically, stresses in the solid body, due to the stresses a crack propagating in the solid body along the detachment plane, which crack separates the layer of solid material from the solid body.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: March 17, 2020
    Assignee: Siltectra GmbH
    Inventors: Wolfram Drescher, Jan Richter, Christian Beyer
  • Patent number: 10593660
    Abstract: The present invention discloses an array substrate which includes a peripheral driving circuit region. The peripheral driving circuit includes a first metal layer, a first insulating layer and a second metal layer sequentially formed on a base substrate. There is a signal transmission line provided in the driving circuit region. The signal transmission line is connected in series with a current limiting unit. The current limiting unit includes M first metal lines formed in the first metal layer at intervals and N second metal lines formed in the second metal layer at intervals. The M first metal lines and the N second metal lines are alternately connected in series with each other through vias provided in the first insulating layer, and M and N are integers greater than 1, respectively. The present invention further comprises a display device including an array substrate mentioned above.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: March 17, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Yu Zhao, Wonjoong Kim
  • Patent number: 10586838
    Abstract: Provided is a display device including a first sub-pixel, a second sub-pixel adjacent to the first sub-pixel. The first sub-pixel and the second sub-pixel each include a semiconductor film, a gate electrode, a gate insulating film, an interlayer insulating film, and a leveling film and further possesses a light-emitting element located over the leveling film. The display device has a partition wall located between the first sub-pixel and the second sub-pixel and a trench passing through the leveling film.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: March 10, 2020
    Assignee: Japan Display Inc.
    Inventor: Masakazu Gunji
  • Patent number: 10580933
    Abstract: Disclosed herein is a highly reliable light emitting diode. In the light emitting diode, a connector connecting light emitting cells to each other is spaced apart from bump pads in a lateral direction so as not to overlap each other. Accordingly, it is possible to provide a chip-scale flip-chip type light emitting diode having good properties in terms of heat dissipation performance and electrical reliability.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: March 3, 2020
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Se Hee Oh, Jong Kyu Kim, Hyun A Kim
  • Patent number: 10573845
    Abstract: A display device includes: a resin layer on the circuit layer including a groove surrounding and separating a display area; light-emitting elements on an upper surface of the resin layer so as to emit light with luminances controlled by the currents; a sealing layer covering the light-emitting elements; a second substrate above the sealing layer; a sealing material provided between the sealing layer and the second substrate so as to surround the display area and the groove; and a filling layer surrounded by the sealing material between the sealing layer and the second substrate. The groove is formed along a line describing a shape that is inscribed in a rectangle and not in contact with corners of the rectangle as viewed in a direction vertical to the upper surface of the resin layer.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: February 25, 2020
    Assignee: Japan Display Inc.
    Inventors: Takayasu Suzuki, Toshihiro Sato
  • Patent number: 10573531
    Abstract: A method of manufacturing a semiconductor device includes forming a first photoresist film over a substrate, exposing a first pattern including an alignment pattern in a first region, forming, on the substrate, an alignment mark corresponding to the exposed alignment pattern, forming a second photoresist film over the substrate on which the alignment mark is formed, dividing a second pattern into a plurality of regions and exposing the divided regions separately in a second region while performing positioning with respect to the alignment mark, and developing the second photoresist film and forming the second photoresist film having the second pattern, wherein at least a part of the second region is located outside an effective exposure region of an exposure apparatus in exposure of the first pattern.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: February 25, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Shuji Tobashi, Masayuki Tsuchiya
  • Patent number: 10573638
    Abstract: An ESD protection circuit assembly for use in a CMOS manufacturing process is disclosed to include an I/O circuit including a power I/O unit and a signal I/O unit, and an electrostatic discharge clamp circuit connected to the power I/O unit and including a P-type substrate, a series of low voltage P-type structures arranged on the P-type substrate, a plurality of low voltage N-type wells formed on the P-type substrate corresponding to the low voltage P-type structures and a first P-type heavily doped area and a second P-type heavily doped area formed in each low voltage N-type well. By using a series of low voltage P-type structures to provide high ESD tolerance, the ESD protection circuit assembly can be more effectively utilized in the same circuit layout area.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: February 25, 2020
    Assignee: EGALAX_EMPIA TECHNOLOGY INC.
    Inventors: Po-Chuan Lin, Shr-Hau Shiue
  • Patent number: 10566224
    Abstract: Methods, systems and devices for protecting partially processed electronic parts, are disclosed. In some embodiments, a method for protecting electronic parts includes applying a first protective sheet on one or more partially-processed semiconductor devices, removing the first protective sheet, and performing a semiconductor-processing operation on the one or more partially-processed semiconductor devices. In some embodiments, a semiconductor processing system for protecting electronic parts includes one or more partially-processed semiconductor devices, and a first protective sheet applied on the one or more partially-processed semiconductor devices, the first protective sheet being subsequently removed, and a semiconductor-processing operation being performed on the one or more partially-processed semiconductor devices.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: February 18, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventor: John D Steeves
  • Patent number: 10559649
    Abstract: A capacitor structure is described. A metal insulator metal capacitor in an integrated circuit device includes a first dielectric layer on a substrate. The first dielectric layer has a linear trench feature in which the capacitor is disposed. A bottom capacitor plate is in a lower portion of the trench. The bottom capacitor plate has an extended top face so that the extended top face extends upwards in a central region of the bottom capacitor plate metal relative to side regions. A high-k dielectric layer is disposed over the extended top face of the bottom capacitor plate. A top capacitor plate is disposed in a top, remainder portion of the trench on top of the high-k dielectric layer.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Theodorus E Standaert
  • Patent number: 10553671
    Abstract: Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: February 4, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Jonghae Kim, Daeik Daniel Kim, Changhan Hobie Yun, Mario Francisco Velez
  • Patent number: 10541128
    Abstract: A method of forming a semiconductor device and resulting structures having an etch-resistant interlayer dielectric (ILD) that maintains height during a top epitaxy clean by forming a dielectric layer on a semiconductor structure; wherein the dielectric layer includes a first dielectric material; converting at least a portion of the dielectric layer to a second dielectric material; and exposing the portion of the dielectric layer to an etch material; wherein the etch material includes a first etch characteristic defining a first rate at which the etch material etches the first dielectric material; and wherein the etch material further includes a second etch characteristic defining a second rate at which the etch material etches the portion of the dielectric layer; wherein the first rate is different than the second rate.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: January 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10535634
    Abstract: Embodiments herein relate to a system in package (SiP). The SiP may have a first layer of one or more first functional components with respective first active sides and first inactive sides opposite the first active sides. The SiP may further include a second layer of one or more second functional components with respective second active sides and second inactive sides opposite the second active sides. In embodiments, one or more of the first active sides are facing and electrically coupled with one or more of the second active sides through a through-mold via or a through-silicon via.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: January 14, 2020
    Assignee: INTEL CORPORATION
    Inventors: Vijay K. Nair, Chuan Hu, Thorsten Meyer
  • Patent number: 10529626
    Abstract: A semiconductor structure and fabrication method are provided. The method includes: providing a base substrate; forming doped epitaxial layers in the base substrate on sides of a gate structure on the base substrate; forming an interlayer dielectric layer over the base substrate and above the doped epitaxial layers; forming a contact opening in the interlayer dielectric layer; forming a dielectric layer on and surrounding each doped epitaxial layer; applying a repairing process on the dielectric layer; after the repairing process, forming a metal layer on the dielectric layer; and after forming the metal layer in the contact opening, forming a conductive plug in the contact opening.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: January 7, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Yong Li
  • Patent number: 10515862
    Abstract: Embodiments may also include a residual chemical reaction diagnostic device. The residual chemical reaction diagnostic device may include a substrate and a residual chemical reaction sensor formed on the substrate. In an embodiment, the residual chemical reaction sensor provides electrical outputs in response to the presence of residual chemical reactions. In an embodiment, the substrate is a device substrate, and the sensor is formed in a scribe line of the device substrate. In an alternative embodiment, the substrate is a process development substrate. In some embodiments, the residual chemical reaction sensor includes, a first probe pad, wherein a plurality of first arms extend out from the first probe pad, and a second probe pad, wherein a plurality of second arms extend out from the second probe pad and are interdigitated with the first arms.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: December 24, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Leonard Tedeschi, Benjamin Schwarz, Changhun Lee, Ping Han Hsieh, Adauto Diaz, Daniel T. McCormick
  • Patent number: 10515872
    Abstract: A transistor having an emitter, a base, and a collector, the transistor includes a substrate, a collector contact, a metallic sub-collector coupled to the collector contact, and the metallic sub-collector electrically and thermally coupled to the collector, and an adhesive layer between the substrate and the metallic sub-collector, the adhesive layer bonded to the substrate and in direct contact with the substrate and bonded to the metallic sub-collector and in direct contact with the metallic sub-collector, wherein the adhesive layer comprises an electrically conductive material.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: December 24, 2019
    Assignee: HRL Laboratories, LLC
    Inventors: James Chingwei Li, Yakov Royter, Pamela R. Patterson, Donald A. Hitko
  • Patent number: 10504733
    Abstract: A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: December 10, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sebastian Meier, Helmut Rinck, Mike Mittelstaedt
  • Patent number: 10504941
    Abstract: The present invention provides an array substrate comprising a substrate, a metal conductive film layer, and an anti-reflective film layer located between the substrate and the metal conductive film layer, and a method for manufacturing the same, as well as a display device. The method comprises step S1: forming an anti-reflective film layer on a substrate by adjusting the reaction power and/or reactive gas flow during the formation of film by the chemical vapor deposition process; and step S2: forming a metal conductive film layer on the substrate finished in step S1. Through the preparation method of the array substrate, the anti-reflective film layer can have a sand-like granulation structure, such that light reflected from the metal conductive film layer can be blocked, thereby weakening or avoiding the light reflected from the surface of the metal conductive film layer, further improving the display effect of the array substrate.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: December 10, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Liangliang Li, Huibin Guo, Shoukun Wang, Yuchun Feng, Yao Liu