Abstract: Low resistance interconnect lines and methods for fabricating them are described herein. IC fabrication processes are used to create interconnect lines of Al and Cu layers. The Cu layer is thinner than in the known art, but in combination with the Al layer, the aggregate Cu/Al resistance is lowered to a point where it is comparable to that of a very thick Cu layer, without the additional cost and yield problems caused by using a thicker Cu deposition. Fuses for memory repair can also be fabricated using the methods taught by the present invention with only small variations in the process.
Type:
Grant
Filed:
November 27, 2001
Date of Patent:
November 9, 2004
Assignee:
LSI Logic Corporation
Inventors:
Chuan-cheng Cheng, Sethuraman Lakshminarayanan, Peter J. Wright, Hong Ying