Abstract: Disclosed is a CMOS image sensor, which can minimize a reflectance of light at an interface between a photodiode and an insulating film, thereby enhancing image sensitivity. Such a CMOS image sensor includes a substrate provided with a photodiode consisting of Si, an insulating film consisting of SiO2 and formed on the substrate, an anti-reflection film interposed between the substrate and the insulating film, and metal interconnections, color filters and micro lenses constituting individual unit pixels. The semi-reflection film has a refraction index value between those of the Si photodiode and the SiO2 insulating film.
Abstract: P type semiconductor well regions 8 and 9 for device separation are provided in an upper and lower two layer structure in conformity with the position of a high sensitivity type photodiode PD, and the first P type semiconductor well region 8 at the upper layer is provided in the state of being closer to the pixel side than an end portion of a LOCOS layer 1A, for limiting a dark current generated at the end portion of the LOCOS layer 1A. In addition, the second P type semiconductor well region 9 at the lower layer is formed in a narrow region receding from the photodiode PD, so that the depletion layer of the photodiode PD is prevented from being obstructed, and the depletion is secured in a sufficiently broad region, whereby enhancement of the sensitivity of the photodiode PD can be achieved.
Abstract: A first insulator film and a first polysilicon film are formed on first and second element regions of a semiconductor substrate. The first insulator film and first polysilicon film are removed from the second element region. A second insulator film is formed on the second element region from which the first insulator film and first polysilicon film are removed, and a second polysilicon film is formed on the second insulator film. The first polysilicon film is processed, forming a first gate electrode at the first element region. The second polysilicon film is processed, forming a second gate electrode at the second element region. A silicon nitride film is removed from an element-isolation region. A metal film is formed on the region from which the silicon nitride film has been removed, and connects the first and second gate electrodes.
Abstract: A semiconductor memory integrated circuit includes a plurality of pads; a peripheral circuit having a plurality of control circuits which are arranged at locations adjacent to the plurality of the pads and receive a plurality of input signals to generate a plurality of output signals in response to a plurality of control signals, respectively; and a plurality of fuse circuits for generating the plurality of the control signals, said fuse circuits being arranged between the plurality of the pads and the peripheral circuit. Since the integrated circuit has the fuse circuits at a location adjacent to the pads, the characteristics of the IC can be changed even after the package test when a small region is opened.
Abstract: An anisotropic conductive sheet manufactured through improved manufacturing steps and a method of manufacturing the same. Conductive portions are unevenly arranged in a nonconductive elastomer having fluidity and serving as a matrix, the conductive portions highly densely containing the conductive particles having a specific gravity greater than that of the matrix component, the conductive particles are unevenly dispersed to form substantially nonconductive portions, and the conductive portions and the nonconductive portions are integrally cured to mold anisotropic conductive pieces. The anisotropic conductive pieces are so laminated that the conductive portions and the nonconductive portions are alternately arranged thereby to obtain a first laminate, and the first laminate is cut maintaining a predetermined thickness to obtain a zebra-like sheet.
Abstract: This invention is to provide an ultra-miniaturized, thin-sized memory card provided with a mechanism for preventing a wrong insertion to a memory card slot. A multi-function memory card is composed of a card body and a cap for housing the card body. The card body is made of mold resin that encapsulates plural semiconductor chips mounted on a main surface of a wiring substrate. The card body is housed into the cap with the back face of the wiring substrate facing outward. Guide channels are provided at both side faces of the cap for preventing that the card is inserted upside down. Further, a convex section is provided at the trailing edge of the cap for preventing that the card is inserted in the wrong direction.
Abstract: A semiconductor device includes a semiconductor substrate with a trench; a capacitor; a collar oxide film arranged on a portion of a side of the trench above the capacitor; a storage node arranged on a side of the collar oxide film in an upper portion of the trench and electrically connected to a storage electrode of the capacitor; a select transistor provided on a surface of the semiconductor substrate and having a source region in contact with the trench; a spacer covering a side of the source region; and a surface strap contact arranged upon the spacers, the source region and the storage node.
Abstract: A chip compressing mechanism is provided. The chip compressing mechanism essentially comprises a loading component, a head component and a gimbal. The head component is disposed under the loading component, with a gap in-between. The gimbal is disposed between the loading component and the head component to support the gap therebetween.
Abstract: Disclosed is a method of manufacturing a flash memory device. In a flash memory device using a SA-STI scheme, a trench for isolation is buried with oxide. A field oxide film is then formed by means of a polishing process. Next, field oxide films of a cell region and a low-voltage transistor region are selectively etched by a given thickness. As EFH values of the cell region, the low-voltage transistor region and the high-voltage transistor region become same or similar, it is possible to secure stability of a subsequent process.
Abstract: There is provided a method of manufacturing a semiconductor device in which interconnect capacitance is restrained. The semiconductor device 200 comprises a semiconductor substrate; a second interconnect insulating film 216 constituted of a ladder-type hydrogen siloxane formed on the semiconductor substrate; a second protection film 217 provided on the second interconnect insulating film 216; and an upper interconnect 270 formed in the second interconnect insulating film 216 and the second protection film 217. The second interconnect insulating film 216 is constituted of for example an L-Ox™ (trademark) film, and the second protection film 217 is constituted of for example a silicon oxide film.
Abstract: A semiconductor device has a structure that reduces the parasitic capacitance by using a film with a low relative dielectric constant as the side wall material of the gate. The material with a low relative dielectric constant is preferably a material whose relative dielectric constant is less than the relative dielectric constant of an oxide film, i.e., less than about 3.9.
Abstract: The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates to the FIN MOSFFET structure which is formed using method of the present invention.
October 28, 2003
Date of Patent:
February 6, 2007
International Business Machines Corporation
Jeffrey P. Gambino, Jerome B. Lasky, Jed H. Rankin
Abstract: A solid state imaging device including: a photoelectric conversion element generating photo-generated charges corresponding to incident light; an accumulation well accumulating photo-generated charges; a modulation well storing photo-generated charges from the accumulation well; a modulation transistor whose channel threshold voltage is controlled by the stored photo-generated charges and that outputs a pixel signal corresponding to the photo-generated charges; a transfer control element changing the potential barrier of a transfer channel between the accumulation well and the modulation well to control transfer of the photo-generated charges; and an unwanted charges discharge control element controlling the potential barrier of an unwanted charges discharge channel coupled to the accumulation well, and discharging charges which overflow from the accumulation well through the unwanted charges discharge channel during all periods other than the transfer period when photo-generated charges are transferred from
Abstract: A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t2 of the gate electrode 10 on the second gate oxide films 6A and 6B is thinner than the thickness t1 of the prior art. Therefore, the height gap h2 between the gate electrode 10 and the N+type source layer 11 and the height gap h2 between the gate electrode 10 and the N+type drain layer 12 become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film 13.
Abstract: A vertical MOSFET has a substrate of a first conductivity type. A channel region of a second conductivity type is diffused into the substrate. A gate is disposed at least partially over the channel region. A source region of a second conductivity type is disposed proximate to the gate and adjacent to the channel region. The channel region includes a depletion implant area proximate to the gate. The depletion implant species is of the second conductivity type to reduce the concentration of the first conductivity type in the channel region without increasing the conductivity in the drain/drift region.
February 26, 2002
Date of Patent:
August 15, 2006
International Rectifier Corporation
Kyle Spring, Jianjun Cao, Thomas Herman
Abstract: To reduce the on-resistance in a semiconductor device, such as a trench lateral power MOSFET, a trench etching region forms a mesh pattern in which a first trench section, formed in an active region, and a second trench section, formed in a gate region for leading out gate polysilicon to a substrate surface, intersect each other. An island-like non-trench region, which is left without being subjected to etching, is divided into a plurality of smaller regions by one or more third trench section that connect with the first and second trench sections that form the mesh pattern. In each non-trench region, a contact section for connecting a drain region (or a source region) and an electrode is formed so as to be spread over all of the smaller regions in the non-trench region.
November 24, 2003
Date of Patent:
April 25, 2006
Fuji Electric Device Technology Co., Ltd.
Abstract: An image pick-up unit includes an image pick-up device; and a plurality of optical filters which are cemented together in layers and positioned in front of the image pick-up device. At least two optical filters among the plurality of optical filters, which have different optical properties, are different in shape from each other.
Abstract: A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.
Abstract: Disclosed is a method for fabricating capacitors for semiconductor devices. This method includes the steps of forming a lower electrode on an understructure of a semiconductor substrate, depositing an amorphous TaON thin film over the lower electrode, annealing the deposited amorphous TaON thin film in an NH3 atmosphere, and repeating the deposition of the amorphous TaON thin film and the annealing of the deposited amorphous TaON thin film at least one time, thereby forming a TaON dielectric film having a multi-layer structure, and forming an upper electrode over the TaON dielectric film. The TaON dielectric film having a multi-layer structure exhibits a dielectric constant that is superior to those of conventional dielectric films. Accordingly, the TaON dielectric film of the invention can be used for capacitors in next generation semiconductor memory devices of grade 256 MB and higher.