Abstract: The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal interconnect line fabrication, a TiN thin film combined with an Al intermediate layer is used as a diffusion barrier on trench or via walls. For the formation, Al is deposited on the TiN thin film followed by copper filling the trench. Al diffuses to TiN layer and reacts with oxygen or nitrogen, which will stuff grain boundaries efficiently, thereby blocking the diffusion of copper successfully.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of fabricating or manufacturing MEMS having mechanical structures that operate in controlled or predetermined mechanical damping environments. In this regard, the present invention encapsulates the mechanical structures within a chamber, prior to final packaging and/or completion of the MEMS. The environment within the chamber containing and/or housing the mechanical structures provides the predetermined, desired and/or selected mechanical damping. The parameters of the encapsulated fluid (for example, the gas pressure) in which the mechanical structures are to operate are controlled, selected and/or designed to provide a desired and/or predetermined operating environment.

Abstract: A triplet light emitting device which has high efficiency and improved stability and which can be fabricated by a simpler process is provided by simplifying the device structure and avoiding use of an unstable material. In a multilayer device structure using no hole blocking layer conventionally used in a triplet light emitting device, that is, a device structure in which on a substrate, there are formed an anode, a hole transporting layer constituted by a hole transporting material, an electron transporting and light emitting layer constituted by an electron transporting material and a dopant capable of triplet light emission, and a cathode, which are laminated in the stated order, the combination of the hole transporting material and the electron transporting material and the combination of the electron transporting material and the dopant material are optimized.

Abstract: A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.

Abstract: Single-walled carbon nanotube transistor and rectifying devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for source and drain of a transistor are provided at opposite ends of the single-walled carbon nanotube devices. A gate region may be provided one end or both ends of the porous structure. The gate electrode may be formed into the porous structure. A transistor of the invention may be especially suited for power transistor or power amplifier applications.

Abstract: A semiconductor device comprises a semiconductor element and a support body made of a stack of ceramic layers having a recess in which electrical conductors are electrically connected with the semiconductor element, wherein at least a part of a top face of a recess side wall is covered by a resin, thereby providing a light emitting device.

Abstract: An improved fuse link structure and fuse blowing method, the fuse-link structure including a plurality of elongated fuse-link members comprising polysilicon electrically connected in parallel according to a common input Voltage contact and common output current contact to form a fuse-link structure; and, wherein at least a portion of the plurality of elongated fuse-link comprise a different electrical resistance with respect to one another according to a variable condition selected from the group consisting of critical dimension, polysilicon doping condition, and silicide agglomeration condition.

Abstract: A high-voltage transistor device with an interlayer dielectric (ILD) etch stop layer for use in a subsequent contact hole process is provided. The etch stop layer is a high-resistivity film having a resistivity greater than 10 ohm-cm, thus leakage is prevented and breakdown voltage is improved when driving a high voltage greater than 5V at the gate site. A method for fabricating the high-voltage device is compatible with current low-voltage device processes and middle-voltage device processes.

Abstract: In accordance with an embodiment of the invention, a superjunction semiconductor device includes an active region and a termination region surrounding the active region. A central vertical axis of a boundary column of a second conductivity type material defines the boundary between the active region and the termination region. The active and termination regions include columns of first and second conductivity type material alternately arranged along a horizontal direction in a semiconductor region having top and bottom surfaces. At least one of the columns of the first conductivity type material in the termination region has a different width than a width of the columns of the first conductivity type material in the active region.

Abstract: Bundled cables and a method for maintaining a plurality of cables together during use and installation and for allowing the cables to be easily separated for termination or connectorization. The bundled cables include a plurality of cables and a central flexible strip coated with a thermoplastic heat-sealable resin for semi-permanently bundling the cables. In operation, the strip is heated to activate the heat-sealable resin. The cables are then placed in contact with the strip to bind to the strip as the heat-sealable resin cools. The bond created by the heat-sealable resin is strong enough to hold the cables together during installation and use but allows the cables to be easily separated in whole or in part from the bundle.

Abstract: A semiconductor device includes an interface chip and a plurality of DRAM chips consecutively layered on the interface chip. A plurality of source electrodes, a plurality of ground electrodes, and a plurality of signal electrodes penetrate DRAM chips and interconnect the DRAM chips to the interface chip, which is connected to an external circuit. Each source electrode, a corresponding signal electrode and a corresponding ground electrode are arranged adjacent to one another in this order to reduce electromagnetic noise during operation of the DRAM chip.

Abstract: An improved imaging array (and corresponding method of operation) includes a plurality of heterojunction thyristor-based pixel elements disposed within resonant cavities formed on a substrate. Each thyristor-based pixel element includes complementary n-type and p-type modulation doped quantum well interfaces that are spaced apart from one another. Incident radiation within a predetermined wavelength resonates within the cavity of a given pixel element for absorption therein that causes charge accumulation. The accumulated charge is related to the intensity of the incident radiation. The heterojunction-thyristor-based pixel element is suitable for many imaging applications, including CCD-based imaging arrays and active-pixel imaging arrays.

Abstract: The present invention is related to a method for forming a storage node of a semiconductor device. The method includes the steps of: (a) forming a plurality of bit line patterns, each including a wire and a hard mask sequentially stacked on a surface of a substrate structure; (b) sequentially forming a first barrier layer and a first inter-layer insulation layer along a profile containing bit line patterns until filling spaces between the bit line patterns; (c) etching the first inter-layer insulation layer until a partial portion of the first inter-layer insulation layer remains on each space between the bit line patterns; (d) forming a second barrier layer on the first inter-layer insulation layer and the first barrier layer; and (e) etching the first and the second barrier layers and the remaining first inter-layer insulation layer to expose a surface of the substrate structure disposed between the bit line patterns.

Abstract: Apparatuses and methods for forming displays are claimed. This invention relates to a display which may be conformal and which can receive information in order to alter or configure the display. In one embodiment, a flexible layer may be made to receive an array of blocks which drive a display material to provide an alterable or configurable display. This display is coupled to a receiver which receives data and drives the data onto the blocks causing the display to change. The receiver (and blocks) may be powered by a signal from a transmitter which beams the information to the receiver. The receiver in turn controls the update of the display information on the display. Another embodiment of the invention has a receiver coupled to each block. The receiver also may be independent from the block and may be deposited onto the flexible layer.

Abstract: The liquid crystal display device of this invention includes a plurality of picture element regions each defined by a first electrode provided on a face of a first substrate facing a liquid crystal layer and a second electrode provided on a second substrate so as to oppose the first electrode via the liquid crystal layer sandwiched therebetween. In each of the picture element regions, the first electrode has a plurality of openings and a solid portion, the liquid crystal layer is in a vertical orientation state when no voltage is applied between the first electrode and the second electrode, and when a voltage is applied between the first electrode and the second electrode, a plurality of liquid crystal domains each in a radially-inclined orientation state are respectively formed in the plurality of openings and the solid portion by inclined electrode fields generated at respective edge portions of the openings of the first electrode.

Abstract: An integrated circuit formed on a semiconductor substrate and configured to accommodate higher voltage devices and low voltage devices therein. In one embodiment, the integrated circuit includes a transistor having a gate located over a channel region recessed into a semiconductor substrate, and a source/drain including a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The transistor also includes an oppositely doped well located under and within the channel region. The transistor still further includes a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region. The integrated circuit also includes a driver switch of a driver formed on the semiconductor substrate.

Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.

Abstract: A semiconductor device includes a substrate having an active layer, an element region provided in the active layer, a P-type semiconductor region provided in the element region, and first and second N-type semiconductor regions provided in the element region, located on the sides of the P-type semiconductor region, respectively and spaced in a first direction. The device has an N-type MOS transistor and first and second P-type MOS transistors. The N-type MOS transistor has a first gate electrode provided on the P-type semiconductor region. The first P-type MOS transistor has a second gate electrode provided on the first N-type semiconductor region. The second P-type MOS transistor has a third gate electrode provided on the second N-type semiconductor region.

Abstract: A nitride semiconductor light emitting device includes at least a substrate, an active layer formed of a nitride semiconductor containing mainly In and Ga, a p-electrode and an n-electrode. At least one of the p-electrode and n-electrode is electrically separated into at least two regions.