Abstract: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.

Abstract: A method of fabricating a liquid crystal display device is disclosed in the present invention. The method includes forming a thin film transistor in a pixel region and a pad on an edge region of a first substrate, depositing an organic passivation layer over the first substrate, and removing the organic passivation layer in the edge region using a diffraction mask to expose a portion of the pad, wherein the diffraction mask has a slit portion including a plurality of slits having different widths.

Abstract: A method for releasing from underlying substrate material micromachined structures or devices without application of chemically aggressive substances or excessive forces. The method starts with the step of providing a partially formed device, comprising a substrate layer, a sacrificial layer deposited on the substrate, and a function layer deposited on the sacrificial layer and possibly exposed portions of the substrate layer and then etched to define micromechanical structures or devices therein. The etching process exposes the sacrificial layer underlying the removed function layer material. Next there are the steps of cleaning residues from the surface of the device, and then directing high-temperature hydrogen gas over the exposed surfaces of the sacrificial layer to convert the silicon dioxide to a gas, which is carried away from the device by the hydrogen gas.

Abstract: The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal interconnect line fabrication, a TiN thin film combined with an Al intermediate layer is used as a diffusion barrier on trench or via walls. For the formation, Al is deposited on the TiN thin film followed by copper filling the trench. Al diffuses to TiN layer and reacts with oxygen or nitrogen, which will stuff grain boundaries efficiently, thereby blocking the diffusion of copper successfully.

Abstract: In a liquid crystal panel in which pseudo dot inversion driving is performed, the occurrence of flicker or vertical and horizontal strings is prevented by preventing an alignment shift between individual layers during the fabrication of a TFT array from producing a difference between the respective abilities of thin-film TFTs to charge adjacent pixels (61, 62). For this purpose, the liquid crystal display panel is constructed such that two TFTs which are enclosed by two adjacent image signal lines (21, 22) and scan signal lines (3) and adjacent to each other along the signal lines (21, 22) have respective source electrodes (71, 72) adjacent to the different image signal lines (21, 22). The source electrodes (71, 72) and drain electrodes (81, 82) of the two TFTs connected to the adjacent pixels (61, 62) are alternately arranged such that variations caused by the alignment shift in the sizes and areas of overlapping portions between the individual layers of the TFTs are equal or the same.

Abstract: A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of preparing a microemulsion. The method of the present embodiment then recites applying the microemulsion to a surface above which it is desired to form a region of low dielectric constant nanoporous material. Next, the present method recites subjecting the microemulsion, which has been applied to the surface, to a thermal process such that the region of low dielectric constant nanoporous material is formed above the surface.

Abstract: In order to improve the characteristics of the high breakdown voltage MOS, a semiconductor device of the present invention is characterized in that an LDMOS transistor, which comprises a source region 4, a channel region 8, and a drain region 5, and a gate electrode 7 formed on the channel region 8, and a drift region formed between the channel region 8 and the drain region 5, wherein an N?-type low concentration layer 22 serving as the drift region is formed shallowly at least below the gate electrode 7 (first N?-type layer 22A) but formed deeply in a neighborhood of the drain region 5 (second N?-type layer 22B).

Abstract: The present invention is a nitride compound semiconductor laser, in which a cleaved end face is flat, and a breakdown of a laser end face induced during an operation can be suppressed, which consequently enables a life to be prolonged. In the nitride compound semiconductor laser, a stress concentration suppression layer is formed between an active layer and a cap layer.

Abstract: In an integrated pressure sensor including a semiconductor substrate having a p type single crystal silicon substrate and an n type epitaxial layer of which a portion is etched by electrochemical etching to have a diaphragm, an impurity diffusion layer piercing the n type epitaxial layer at least defining the diaphragm is formed for isolation. An etching wire is formed on the surface of the n type epitaxial layer with insulation and the first end of the etching wire extends to the inside of the surface and connected to the n type epitaxial layer. The second opposite end extends to an edge of the semiconductor substrate. The etching wire does not cross the impurity layer inside the surface of the semiconductor substrate to prevent the etching wire from short-circuiting with the impurity diffusion layer during the electrochemical etching.

Abstract: A double gate MOSFET transistor and a method for fabricating it are described. In this case, a semiconductor layer structure of a transistor channel to be formed is embedded in a spacer material and contact-connected by source and drain regions which are filled into depressions that are etched on opposite sides of the semiconductor layer structure. Afterwards, the spacer material is etched out selectively and replaced by the electrically conductive gate electrode material.

Abstract: Liquid crystal in an in-plane switching type active matrix liquid crystal display unit has elastic coefficients K11 and K33 which respectively concern a spray deformation and a bent deformation of the liquid crystal layer, wherein one of the elastic coefficients K11 and K33 is fallen within the range between 6 pN and 25 pN or the range between 5 pN and 20 pN; otherwise, the square root of the product between the elastic coefficients K11 and K33 is fallen within the range between 5 pN and 20 pN, thereby improving the luminance through restricting the spray deformation and/or the bent deformation.

Abstract: An antenna support bracket is provided that preferably strengthens electronic connectors, such as F connectors and the like, by distributing the load or stress applied to an individual connector over all of the connectors in a group of connectors extending from a television or other consumer electronic device, or from an antenna switch mounted therein. In a preferred embodiment, the bracket comprises a thin, elongate body formed of cold rolled steel with a plurality of holes formed therein. The holes, which are spaced apart in a pattern that matches a corresponding group of connectors, are sized to have a diameter slightly largely than the diameters of the connectors to enable the bracket to slide over the connectors.

Abstract: A common electrode substrate has a transparent insulating substrate to be arranged opposite to an array substrate having pixel electrodes formed in respective pixel regions that are defined by a plurality of gate bus lines and drain bus lines. The substrate holds a liquid crystal having negative dielectric anisotropy. A common electrode is formed on the transparent insulating substrate; alignment regulating structures having linear protrusions are formed on the common electrode; and a light shield film is formed on the transparent insulating substrate with overlap regions that overlap the pixel electrodes when viewed in the direction perpendicular to a surface of the transparent insulating substrate, so as to shield, from light, alignment defective regions of the liquid crystal formed in regions of end portions of the pixel electrodes.

Abstract: In a semiconductor device in which a source/drain and a wiring layer are connected to each other through an associated buried conductive layer, a separation width of the buried conductive layer on a upper portion of a gate electrode is made small in order to manufacture a highly reliable and fine MOS transistor. After a silicon oxide film has been formed on a first polycrystalline silicon film so as to be aligned with a width of a gate electrode, a second polycrystalline silicon film formed on the whole surface of a substrate is selectively etched away so as to be left only on both side faces of a pattern of the silicon oxide film. Thereafter, the first polycrystalline silicon film is separated with a width which is smaller than that of the gate electrode by a width of a pattern of the second polycrystalline silicon film. In such a way, the buried conductive layer including the first and second polycrystalline silicon films is formed.

Abstract: The present invention relates to a semiconductor LED device comprising a pumping layer with high light emitting efficiency and an active layer with smaller bandgap converting the absorbed light into any kinds of light of wavelength as required, which generates light from the AlGaInN pumping layer containing less In, projects the rays of light on the active layer containing more In, lets the required light of wavelength emit and decreases the blue shift caused by electric current, thereby increasing the light emitting efficiency and emitting lights with more than two wavelengths from one Led device. This invention enables to obtain various light of wavelength from one device and form the element through only one epitaxy process, thereby increasing reproductivity, yield, and efficiency by not using the fluorescent materials lowering the efficiency when forming white light.

Abstract: A method of forming a semiconductor structure (see e.g., FIG. 3) includes forming a silicon (e.g., polysilicon) layer 14. The silicon layer 14 is patterned and etched so that at least one sidewall 20 is exposed. An oxygen bearing species (e.g., O2+) is then implanted into the sidewall 20 of the silicon layer 14. In the preferred embodiment, the oxygen bearing species is implanted at an acute angle relative to the plane of the silicon layer 14.

Abstract: In accordance with the objectives of the invention a new method is provided for creating air gaps in a layer of IMD. First and second layers of dielectric are successively deposited over a surface; the surface contains metal lines running in an Y-direction. Trenches are etched in the first and second layer of dielectric in an X and Y-direction respectively. The trenches are filled with a layer of nitride and polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. Openings are created through the thin layer of oxide that align with the points of intersect of the nitride in the trenches in the layers of dielectric. The nitride is removed from the trenches by a wet etch, thereby opening trenches in the layers of dielectric with both sets of trenches being interconnected. The openings in the thin layer of oxide are closed, leaving a network of trenches containing air in the two layers of dielectric.

Abstract: A method of simultaneously forming differential gate oxide for both high and low voltage transistors using a two-step wet oxidation process is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas and wherein there is at least one low voltage area in which a low voltage transistor will be formed and at least one high voltage area in which a high voltage transistor will be formed. The surface of the semiconductor substrate is wet oxidized to form a first layer of gate oxide on the surface of the semiconductor substrate in the active areas. The low voltage active area is covered with a mask. The surface of the semiconductor substrate is wet oxidized again where it is not covered by the mask to form a second layer of gate oxide under the first gate oxide layer in the high voltage active area. The mask is removed.

Abstract: In an integrated pressure sensor including a semiconductor substrate having a p type single crystal silicon substrate and an n type epitaxial layer of which a portion is etched by electrochemical etching to have a diaphragm, an impurity diffusion layer piercing the n type epitaxial layer at least defining the diaphragm is formed for isolation. An etching wire is formed on the surface of the n type epitaxial layer with insulation and the first end of the etching wire extends to the inside of the surface and is connected to the n type epitaxial layer. The second opposite end extends to an edge of the semiconductor substrate. The etching wire does not cross the impurity layer inside the surface of the semiconductor substrate to prevent the etching wire from short-circuiting with the impurity diffusion layer during the electrochemical etching.

Abstract: A method for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization or permittivity by means of ion bombardment resulting in a texture with higher ferroelectric polarization or permittivity which is normally energetically disfavored.