Abstract: A method of manufacturing an array substrate of a display is provided. The method includes forming a first bank material layer on a first substrate, wherein a material of the first bank material layer includes hydrophobic element; patterning the first bank material layer to form a first bank having at least one first concave; forming a first electrode on the first bank and in the first concave after the step of patterning the first bank material layer to form the first bank; and forming an color layer on the first electrode.

Abstract: Capacitive coupling between a gate electrode and underlying portions of the source and drain regions can be enhanced while suppressing capacitive coupling between the gate electrode and laterally spaced elements such as contact via structures for the source and drain regions. A transistor including a gate electrode and source and drain regions is formed employing a disposable gate spacer. The disposable gate spacer is removed to form a spacer cavity, which is filled with an anisotropic dielectric material to form an anisotropic gate spacer. The anisotropic dielectric material is aligned with an electrical field such that lengthwise directions of the molecules of the anisotropic dielectric material are aligned vertically within the spacer cavity. The anisotropic gate spacer provides a higher dielectric constant along the vertical direction and a lower dielectric constant along the horizontal direction.

Abstract: When a test handler loads semiconductor devices of user trays onto a test tray, the test handler adjusts a front/rear pitch or a right/left pitch between the semiconductor devices, adjusts the right/left pitch or the front/rear pitch, and loads the semiconductor devices. The test handler can sequentially adjust individually the front/rear pitch and the right/left pitch between the semiconductor devices, thereby reducing the apparatus weight and the loading time.