Abstract: This patent relates to user devices that have user-selectable operating systems. One implementation can include primary storage having multiple compressed operating systems stored thereon in inoperable form. This implementation can also include a processor configured to execute a multi-option boot loader configured to receive a user selection of an individual operating system. The multi-option boot loader is configured to install a file folder structure on the primary storage in a configuration specific to the individual operating system and to install the individual operating system in an operable form on the primary storage relative to the file folder structure.

Abstract: A method for detecting and classifying powered devices in power over Ethernet/non-power over Ethernet applications is described. In one or more implementations, the method includes deactivating a non-power over Ethernet component for a predetermined time period. The method also includes activating an isolation switch of a powered device after the predetermined time period has elapsed since no characteristic impedance associated with the powered device has been detected.

Abstract: Methods and apparatus for datacenter power management optimization are disclosed. Metrics, including workload data, thermal measurements and the like are collected from numerous endpoints within a datacenter. System profiles of a plurality of servers, and application workload profiles for various workloads, are stored. Based on analysis of collected metrics, power optimization operations comprising either workload scheduling operations, power configuration change operations, or both, are initiated.

Abstract: A network node has an interface which has different modes of operation, including at least a power saving mode and a normal operating mode. The node has a power saving mode management module for maintaining information about whether the interface is in the power saving mode of operation. The power saving mode management module is able to make available to one or more layers higher than the physical layer of the interface information about whether the interface is in the power saving mode of operation.

Abstract: A method includes requesting a time maintained in a first clock domain, receiving, in a second clock domain, a first time value from the first clock domain in response to requesting the time maintained in the first clock domain, determining, in the second clock domain, a latency associated at least with receiving the first time value from the first clock domain, and determining a second time value based on the first time value and the determined latency.

Abstract: Technologies for local power gate (LPG) interfaces for power-aware operations are described. A processor includes locally-gated circuitry of a core, main core circuitry of the core, the main core, and local power gate (LPG) hardware. The LPG hardware is to power gate the locally-gated circuitry according to local power states of the LPG hardware. The main core decodes a first instruction of a set of instructions to perform a first power-aware operation of a specified length, including computing an execution code path for execution. The main core monitors a current local power state of the LPG hardware, selects one of the code paths based on the current local power state, the specified length, and a specified threshold, and issues a hint to the LPG hardware to power up the locally-gated circuitry and continues execution of the first power-aware operation without waiting for the locally-gated circuitry to be powered up.

Abstract: A network powered device includes field effect transistors connected as bridge circuit. The bridge circuit includes control circuitry to enable the FETs based on completion of a powered device detection sequence performed by power sourcing equipment coupled to the device via an Ethernet link.

Abstract: The techniques described herein implement an operating system that can reliably process time sensitive information in non real-time manner. Thus, the operating system described herein is capable of processing an instance of time sensitive input during a time period after the instance of time sensitive input is received (e.g., at a future point in time). To accomplish this, the techniques timestamp each instance of time sensitive input when it is received at a device. The techniques then store the timestamped instance of time sensitive input in a temporary queue, and make the timestamped instance available to the operating system at a time period after the time period when it is received, as indicated by the timestamp. Additional techniques described herein prioritize the activation of a driver configured to receive the time sensitive information during a bootup sequence or a reboot sequence.

Abstract: In some embodiments, an equipment unit has a set of visual indicators, a power switch, and a set of compute components. The power switch receives a signal representing a status such that when the status is in a first mode, the power switch provides power to the set of visual indicators and when the status is in a second mode the power switch does not provide power to the set of visual indicators. The compute components are configured to receive power when the power switch does not provide power to the set of visual indicators.

Abstract: A method of staggering lanes in a peripheral component interconnect express (PCI-Express) port is described herein. The method includes initiating the port to enter or exit an electrical idle state. The method also includes forwarding a token to a predetermined lane of the port. Additionally, the method includes turning the predetermined lane ON or OFF by indication to an analog circuit interface. The method also includes forwarding the token to a neighboring lane when a staggering interval timer elapses.

Abstract: A circuit for producing USB host working clock comprises: an internal oscillator, a controllable frequency divider, a frequency multiplier, a USB host interface, and a frequency division controller. According to the frequency multiplier providing clock, the USB host interface configures with USB peripherals for responding. The frequency division controller is connected to the USB host interface and the controllable frequency divider. The USB host interface transmits a response result that the USB host interface configures with USB peripherals for responding to the frequency division controller. According to the USB host interface feeding back the response result, the frequency division controller regulates a frequency dividing ratio of the controllable frequency divider in set scope of the frequency dividing ratio.

Abstract: An information processing apparatus includes a processor configured to detect an unexecuted first thread and an unexecuted second thread; calculate standby power consumption of the first thread in a case of executing the second thread followed by the first thread, based on an execution period of the second thread and standby power consumption per unit time of the first thread; calculate standby power consumption of the second thread in a case of executing the first thread followed by the second thread, based on an execution period of the first thread and standby power consumption per unit time of the second thread; and determine an order of execution of the first thread and the second thread, based on comparison of the standby power consumption of first thread and the standby power consumption of the second thread.

Abstract: Systems and methods for managing current consumption by an electronic device are provided. The electronic device includes first and second clock units. The first clock unit generates a first reference clock signal based on a first current input. The second clock unit generates a second reference clock signal based on a second current input greater than the first current input. The system includes a control module configured to identify an application to be executed. The control module is configured to determine whether the application is associated with a first current consumption level or a second current consumption level greater than the first current consumption level. The control module is configured to select the first or second reference clock signal based on whether the application is determined to be associated with the first or second current consumption level. The system includes circuitry configured to execute the application based on the selection.

Abstract: A method and apparatus for dynamic clock and power gating and decentralized wakeups is disclosed. In one embodiment, an integrated circuit (IC) includes power-manageable functional units and a power management unit. Each of the power manageable functional units is configured to convey a request to enter a low power state to the power management unit. The power management unit may respond by causing a requesting functional unit to enter the low power state. Should another functional unit initiate a request to communicate with a functional unit currently in the low power state, it may send a request to that functional unit. The receiving functional unit may respond to the request by exiting the low power state and resuming operation in the active state.

Abstract: A method for a mobile platform containing a mobile terminal having an operating system includes initializing a plurality of user environments (UEs) on the mobile terminal over the operating system, including a current UE running on the mobile terminal. The plurality of UEs are capable of being switched among one another based on one or more of predetermined conditions without changing the operating system. The method also includes collecting sensing data on certain parameters associated with operation of the mobile terminal, and processing the sensing data to indicate at least one of the predetermined conditions. Further, the method includes determining whether the current UE suits the at least one of the predetermined conditions indicated by processing the sensing data and, when the current UE does not suit the condition of the mobile terminal, switching the current UE to a desired UE from the plurality of UEs.

Abstract: A Multi-Tile Power Management Integrated Circuit (MTPMIC) includes tiles including an MCU/ADC tile and a power manager tile. The power manager tile includes a hibernate circuit and a set of Configurable Switching Power Supply Pulse Width Modulator (CSPSPWM) components. The CSPSPWM, in combination with other circuitry external to the integrated circuit, form a switching power supply. The hibernate circuit is operable in a hibernate mode where the CSPSPWM is disabled and the switching power supply no longer generates a supply voltage. A processor in the MCU/ADC tile writes across a standardized bus to configure the hibernate circuit to wake up after a timer determines a configurable amount of time has lapsed, or to wake up in response to a signal present on a terminal of MTPMIC. The processor enables the hibernate mode causing the switching power supply to no longer provide power to the processor and other circuitry of MTPMIC.