Abstract: A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a gate structure on the fin-shaped structure and the STI and the fin-shaped structure directly under the gate structure includes a first epitaxial layer; forming a source region having first conductive type adjacent to one side of the gate structure; and forming a first drain region having a second conductive type adjacent to another side of the gate structure.