Abstract: A logical design method for a semiconductor integrated circuit includes the steps of: a) generating a circuit at a logical level so as to meet given functions and specifications; b) extracting a critical path, which will cause the longest delay, from the circuit generated in the step a); c) counting how many times a path leading from each input terminal to an output terminal in every logic cell of the circuit has operated; d) calculating a degradation rate associated with the path leading from each said input terminal to the output terminal in each said logic cell on the critical path by reference to the number of times of operation obtained in the step c); and e) exchanging a connection to one of the input terminals of each said logic cell, which terminal is associated with the critical path, with a connection to another one of the input terminals of the logic cell, which terminal is associated with another path corresponding to a lower degradation rate than that of the critical path, by reference to the deg