Abstract: A decoder block includes a number of generic blocks stitched together. The generic blocks have an address line layout that enables the decoders to be addressed with a reduced number of signal lines.

Abstract: An EDAM tool is provided with an OPEC module that performs optical and/or process pre-compensations on an IC mask layout in a streamlined manner, reusing determined corrections for a first area on a second area, when the second area is determined to be equivalent to the first area for OPC purposes. The OPC module performs the correction on the IC mask layout on an area-by-area basis, and the corrections are determined iteratively using model-based simulations, which in one embodiment, include resist model-based simulations as well as optical model-based simulations.

Abstract: A method of converting or translating a layout or schematic netlist to a simulation netlist, comprising the steps of identifying net-shorting elements in the layout or schematic netlist and automatically replacing at least one such net-shorting element with an RC network to generate the simulation netlist.

Abstract: It is, therefore, an object of the present invention to provide a structure and method of blowing fuses in a semiconductor chip that includes creating a design for the chip using a library, generating test data from the design, extracting the fuse related information from the design to prepare a fuse blow table, building the chip with the design data, testing the chip to produce failed data, comparing the fuse blow table to the failed data to determine the fuse blow location data, and blowing the selected fuses based on the fuse blow location data. The extraction method can include creating a fuse map file based upon a correlation between physical pin locations on the chip and different fuse macros within the design, wherein an order of fuses within the fuse blow table matches an order of fuses within the fuse map file.

Abstract: A method of producing semiconductor devices includes bonding one side of an expandable resin wafer sheet with thermosetting adhesive layers on both sides to a back side of a semiconductor wafer, and dividing the semiconductor wafer into semiconductor elements by dicing to form separation grooves; expanding the wafer sheet, widening the separation grooves between the semiconductor elements; positioning one of the semiconductor elements on a die pad of a lead frame to be die-bonded; cutting the wafer sheet opposite the expanded separation grooves surrounding the semiconductor element which has been positioned on the die pad, separating a piece of the wafer sheet with a semiconductor element on the piece of the wafer sheet, and pressing the adhesive surface on the side of the piece of the wafer sheet opposite the semiconductor element onto a surface of the die pad.

Abstract: The present invention aims to provide a field effect transistor which inhibits an aggregation of silicon atoms attendant on heat treatment and has stable source/drain shapes. The field effect transistor according to the present invention is manufactured using a substrate on which a silicon layer, an buried oxide film (BOX film) and an SOI layer are stacked in order. The field effect transistor has an element isolation layer formed in the SOI layer and further includes visored portions provided so as to cover angular portions on the main surface side of an activation layer defined by the element isolation layer.

Abstract: A device for verifying the operation of a functional logic circuit such as a VLSI implements a circuit fictionally equivalent to the functional circuit, and supplies electric signals thereto. The device includes an equivalent logic circuit, a functional equivalent board and an input/output section. The equivalent logic circuit, mounted on an LSI socket board, is composed of programmable logic elements that implement logic specifications of a first part of the verified functional logic circuit to the level of the gate circuit diagram of the first part. The functional equivalent board implements a circuit functionally equivalent to the other part of the functional circuit in point of input and output. The functional equivalent board implements memory and arithmetic operation circuits.

Abstract: System for accurately predicting the outcome of conditional branch instructions subject to execution in a pipelined processor digital computer. The system comprises a series of predictor stages utilizing different prediction algorithms. The stages are linked to successively refine branch predictions only where prediction accuracy from a previous stage is likely to be improved by a subsequent stage. Improvements to each stage and techniques for stage linkage are described.

Abstract: In branch prediction in a superscalar processor, a fetch block address is stored in a program counter (31) to make an access to a prediction table (32) not only when a branch instruction is predicted but also when an execution history (prediction information) of the branch instruction is registered or updated on the basis of the executed result of the branch instruction.

Abstract: A methodology and implementing system are provided in which pipelined read transfers or PRTs are implemented. The PRTs include a request phase and a response phase. The PRT request phase involves a PRT request master delivering to a PRT request target, a source address, a destination address and the transfer size for the data being requested. In the PRT response phase, the PRT request target becomes a PRT response master, i.e. a PCI bus master, and initiates a completion of the transaction that was requested in the originating PRT request. Pipelined read transfers are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlocks.