Abstract: Disclosed is an arbiter circuit for arbitrating a contention between two request signals which simultaneously attain the H (logical high) level indicating a "request". In this arbiter circuit, buffer circuits, having different input logic threshold voltages, are connected to the respective outputs of two three-input NAND gates. The respective outputs of these two buffer circuits, as signals indicating "acknowledgement" or "negative acknowledgement" of the request signals, are derived as final outputs of the arbiter circuit. One of the buffer circuits has an input logic threshold voltage lower than a logic threshold voltage of the two NAND gates, while the other buffer circuit has an input logic threshold voltage set higher than the logic threshold voltage of the NAND gates.

Abstract: An integrated circuit for level shift is a parallel-connected circuit comprised of a first circuit including a first MOS FET of one conductive type, a third MOS FET of another conductive type and a first MOS FET of the other conductive type which are series-connected in this order and a second circuit including a second MOS FET of the one conductive type, a fourth MOS FET of the other conductive type and a second MOS FET of the other conductive type which are series-connected in this order, wherein gates of the first and second MOS FETs of the one conductive type are connected respectively to the output side and input side of an inverter connected to a low voltage electric power source, gates of the third and fourth MOS FETs of the other conductive type both are connected to a reference voltage source, a gate of the first MOS FET of the other conductive type is connected to a common junction point of the fourth MOS FET and the second MOS FET of the other conductive type, a gate of the second MOS FET of the ot

Abstract: Apparatus is disclosed for introducing a precompensation delay in the path of a data signal to be written onto a magnetic medium, such as a floppy or hard disk. The apparatus includes a current controlled oscillator made up of delay elements having current control nodes, and means for controlling the current level being drawn from the current control nodes. The latter means includes three matched voltage controlled current sources having their outputs connected through a current splitter to the current control nodes, and bypass transistors for decoupling two of the voltage controlled current sources in response to a delay selection signal indicating whether the subject data pulse should be precompensated early, nominal or late.

Abstract: A broadband switching circuit has two or more field controlled switch elements coupled in series between an input terminal and an output terminal. A passive, lossy network is coupled between a junction of consecutive switch elements and a virtual around. The off state isolation of the switch elements is improved and signal losses are reduced significantly. When utilized in multichannel switching circuits, only a single switching voltage polarity per channel is required.

Abstract: Between a liquid crystal module and a control circuit for controlling said liquid crystal module, there are provided that a counter circuit for counting down a timing signal given by said control circuit and an exclusive-OR circuit whose inputs are square wave pulses delivered from said counter circuit and square wave pulses given by said control circuit with a period of twice the frame period. The polarity of voltages applied to liquid crystal module is reversed by square wave pulses delivered from the exclusive-OR circuit with frequency higher than the frame frequency.

Abstract: A frequency correction apparatus having a delay line fed by an input signal, the frequency of such signal being corrected a predetermined amount, .DELTA.f. The delay line has a plurality of output taps regularly disposed along the line. The output taps produce a plurality of successively time-delayed signals each one having the frequency of the input signal. A switching network is included for successively coupling each one of the plurality of time-delayed signals to an output terminal of a predetermined coupling change rate related to .DELTA.f, to produce, at such output terminal, an output signal having a frequency shifted from the frequency of the input signal the predetermined amount required for the desired frequency correction. When the taps are successively coupled to the output terminal in a direction along the delay line away from the input to such line, the frequency of the output signal is equal to the frequency of the input shift shifted lower in frequency the amount .DELTA.f.

Abstract: An apparatus for regenerating original signals comprising: means for introducing a first signal that is produced as an original signal passes through a system that cuts off predetermined frequencies; a first circuit means which produces a third signal obtained on an open loop responsive to said first signal and a second signal which is regenerated from a signal of a predetermined frequency that is cut off by said system; and a second circuit means which regenerates the original signal by converting said third signal into a binary signal.

Abstract: An analog input circuit, which samples and holds predetermined components sampled from input signals, has a filter and a sample and hold circuit which are formed as a unitary structure to simplify the circuit structure. For this purpose, the operational amplifier of the filter is constituted by two stages of voltage-follower circuits that are connected in series via a switch, and a holding capacitor is connected to the the switch. When the switch is closed, the holding capacitor assumes the same potential as the output of the filter and when the switch is opened, the holding capacitor maintains the output voltage of the filter.

Abstract: A time signalling device which includes a clock for generating an actual time signal, a time preset circuit for presetting a time to be signalled, a comparator for comparing the actual time with the preset time and producing an output signal when coincidence occurs.