Abstract: The present invention relates to a memory device and specifically the multilevel type with error check and correction function and having a data input (DI), a data output (DO) and an address input (A1) and being of the type comprising first memory, circuit (DM) designed to be accessed by means of address for containing user data, second memory circuit (EM) for containing error data concerning said user data, a control logic (CL) designed to receive in the writing phase from said address input (A1) and the data input (DI) a writing address and user data respectively and to generate error data and to write, the data in the first circuit (DM) and second circuit (EM) respectively and designed to receive in the reading phase from said address input (AI) a reading address and extract corresponding user data and error data and combine them to correct any errors and supply them to the data output (DO) and characterized in that the second, circuit (EM) is the type designed to be accessed by means of content and, the c