Abstract: A network intermediate device and method are provided. The network intermediate device according to an exemplary embodiment of the present invention comprises a data transmitting/receiving part which receives frames which have header error check information, and a control part which controls the data transmitting/receiving part to start forwarding the frame before the entire frame is received by determining whether there are errors in the header using the header error check information. In this case, the frame may comprise a first field in which header error check flag information is recorded to notify whether to perform the forwarding after checking for errors in the header, and a second field in which the header error check information is recorded. If it is confirmed that the check and forward method is applied by the header error check flag information, the control part may verify the header error check information to determine whether errors occur in the header.

Abstract: Disclosed herein is a CRC generator polynomial select method for selecting a generator polynomial to be used in CRC coding and code checking, the method may include a first process of finding largest minimum Hamming distances Max.dmin of codes generated from given polynomials; a second process of finding code lengths n for codes having the largest minimum Hamming distances Max.dmin and determining a range nmin (r, Max.dmin)?n?nmax (r, Max.dmin); a third process of searching all polynomials for specific polynomials generating codes having dmin=Max.dmin in the determined range; and a fourth process of selecting final generator polynomials having a smallest non-zero coefficient count and a lowest code undetected-error probability from the specific polynomials.

Abstract: A method of interleaving blocks of indexed data of varying length is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon a desired Interleaver length L; and adapting the selected basic Interleaver to produce an Interleaver having the desired Interleaver length L.

Abstract: A data partitioning circuit partitions received data and an appended error checking code into a plurality of data lines having a fixed length and a last line. A vector selector inserts a pad vector after the appended error checking code when the last line is less than the first length and not equal to the first fixed length minus a length of the appended error checking code, and selects one of a plurality of error checking vectors, the pad vector having a length providing the last line with the first fixed length when appended thereafter, and the plurality of error checking vectors comprising an initial vector and an error checking code feedback vector. An error checking code calculation circuit performs error checking calculations on the plurality of data lines and the last line to generate an error checking result.

Abstract: Circuits, architectures, methods and algorithms for joint channel-code decoding of linear block codes, and more particularly, for identifying and correcting one or more errors in a code word and/or for encoding CRC (or parity) information. In one aspect, the invention focuses on use of (i) remainders, syndromes or other polynomials and (ii) Gaussian elimination to determine and correct errors. Although this approach may be suboptimal, the present error checking and/or detection scheme involves simpler computations and/or manipulations than conventional schemes, and is generally easier to implement logically.

Abstract: A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called preceding to the modulation encoded bit stream. However, this preceding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before preceding is applied by the precoder. The decoder subsystem operates in the inverse manner.

Abstract: A wireless communication system includes a first communication station configured to operate according to a first communication protocol, and a second communication station capable of operating according to both the first communication protocol and a second communication protocol. When the second communication station transmits a packet according to the second communication protocol, at least a first signal field compliant with the first communication protocol and a second signal field compliant with the second communication protocol are attached to a header of the packet, and the first signal field includes a parity bit. When the second communication station receives a packet from another communication station, the second communication station performs a parity check on the first signal field of the packet, and when no parity error is detected, the second communication station further checks whether content of the first signal field is compliant with the first communication protocol.

Abstract: A method and apparatus for embedded memory security is disclosed. One embodiment protects data in a memory block from unauthorized reading. When writing or reading data to or from the memory block an error correction code is used to calculate an ECC value, wherein the calculation of the ECC value is based on a combination of the data and a access identifier provided to the memory block prior to reading. The access identifier identifies the requesting program. A read error is signalled in case the calculated ECC value does not match a stored value thus indicating an access violation.

Abstract: A signal control circuit and a signal control apparatus that can reduce processing time and can send or receive correct data with reliability. When a data generation block outputs data, a data judgment block judges the number of changed bits by comparing each bit of the data output in the preceding session with the corresponding bit of the data to be sent in the current session and outputs position information indicating the position of each changed bit and the number of changed bits when the number of changed bits has reached a predetermined level. An output control block keeps a time period for stabilizing the change in value of the bit corresponding to the position information when the data is output, and directs a data storage block to send the value of the bit corresponding to the position information to an external circuit after the kept period has passed.

Abstract: A control method includes the steps of storing data in a cache; generating parity data corresponding to the data stored in the cache and storing the parity data in a buffer; writing the data stored in the cache and the parity data stored in the buffer into a plurality of the storage units; reading the data and the parity data from the plurality of storage units; checking error over the read out data by using the read out parity data; storing, if an error is detected in the read out data and the read out parity data, data for reading a plurality of data constituting a stripe in each of the plurality of storage units in the buffer, regenerating parity data by using the plurality of data readout from the storage units; and overwriting the plurality of data and the parity data into the plurality of the storage units.

Abstract: An apparatus and method for transmitting a signal using a bit grouping method in a wireless communication system is disclosed. Interleaved subblocks are maintained, and output bit sequences are modulated in due order after bit grouping and bit selection. The bit grouping method is advantageous in that bit reliability is uniformly distributed.

Abstract: An apparatus is operable to receive a digital video signal transmitted over a channel and comprises an operational module configured to operate in a first mode of operation and in a second mode. The apparatus is configured to switch operation of the operational module from the first mode to the second mode in dependence of an estimate of an environment (condition) of the channel.

Abstract: A digital content transmission and reception system that uses feedback and re-transmission of missing content is described. A content transmission system broadcasts a complete set of digital content to a plurality of content reception systems via a communication link. A content reception system receives a corresponding incomplete set of digital content, determines particular content portions that are missing, and provided feedback indicating the missing content portions to the content distribution system. The content distribution system the re-transmits content based on the feedback.

Abstract: Disclosed is a method for ensuring the integrity of a container to be transmitted to a Digital Video Broadcasting-Handheld (DVB-H) terminal. A DVB-H server divides a container in which data required to deliver broadcasting information is included into one or more sections, extracts a Cycle Redundancy Check (CRC) value related to data of each section, and then creates profile information of the container. The created profile information of the container is used to check the integrity of the container, and is transmitted following the addition of the created profile information to a header part of the container. Hence, the terminal compares data of an actually received container with data of a container which has to be received on the basis of the profile information related to the container, and determines if the data included in the container is lost.

Abstract: In exemplary embodiments, a skewed interleaving function for iterative code systems is described. The skewed interleaving function provides a skewed row and column memory partition and a layered structure for re-arranging data samples read from, for example, a first channel detector. An iterative decoder, such as an iterative decoder based on a low-density parity-check code (LDPC), might employ an element to de-skew the data from the interleaved memory partition before performing iterative decoding of the data, and then re-skew the information before passing decoded samples to the de-interleaver. The de-interleaver re-arranges the iterative decoded data samples in accordance with an inverse of the interleaver function before passing the decoded data samples to, for example, a second channel detector.

Abstract: An information transmitting apparatus is described. An interface includes a first input for a valid data word, a second input for an information to be transmitted, and an output, wherein the interface provides the data word or a data word recognizable as an invalid data word at the output, depending on the information. Accordingly, an information receiving apparatus comprises an interface comprising an input for a data word and an output for an information, wherein the interface derives the information depending on whether the data word is a valid data word or an invalid data word.

Abstract: A system, method and node for unambiguous encoding of Physical Downlink Control Channel (PDCCH) channels in a Long Term Evolution (LTE) telecommunications system to remove detection errors. The method includes the step of modifying a size of a circular buffer by excluding at least one coded bit from the circular buffer. The circular buffer collects interleaved bits from a PDCCH payload having a plurality of bits. The PDCCH payload is encoded with a convolutional code. The bits of the PDCCH payload are then interleaved. The interleaved bits are collected into the modified circular buffer. The bits are then selected from the modified circular buffer for transmission.

Abstract: A method of terminating two or more constituent encoders of a turbo encoder employing a turbo code, comprising the step of: generating tail input bits at each of two or more constituent encoders, including deriving the tail input bits from each of the two or more constituent encoders separately from a contents of shift registers within each of the two or more constituent encoders, after an encoding of information bits by the two or more constituent encoders; puncturing one or more tail output bits such that 1/R output tail bits are transmitted for each of a plurality of trellis branches, wherein R is a turbo code rate employed by the turbo encoder during an information bit transmission. In yet another variation, the step of puncturing the tail output bits further comprises the step of: transmitting, during trellis termination, the tail output bits, only if they are sent from an output branch of one of the two or more constituent encoders that are used during information bit transmission.

Abstract: A method for decoding forward error correction (FEC) encoded data. A stream of units of FEC encoded bits are received, where the units are derived from a transmitted signal, where each unit represents a one-bit data value, and where each unit includes correctness bits. Preferably, the stream of units of FEC encoded bits are decoded by using the quality level of bits to perform soft-decision convolution decoding on the stream of units of FEC bits, where the soft-decision convolution decoding produces, for block decoding, a stream of symbols made up of bits. Subsequences of units that are prone to erroneous soft-decision convolution decoding are detected by determining, for the sub-sequences whether the distribution of quality bits indicate the units are below a threshold level of correctness, and by comparing characteristics of that distribution to a given set of characteristics predetermined to be prone to result in incorrect decoding.

Abstract: A method for communication includes encoding data using at least one Error Correction Code (ECC) to generate first and second output data streams. The first output data stream is processed to generate a first output signal, which has a first acquisition time. The second output data stream is processed to generate a second output signal, which has a second acquisition time that is smaller than the first acquisition time. The first and second output signals are transmitted simultaneously over a communication channel.