Abstract: One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening.

Abstract: A semiconductor device includes at least a first wire pattern, a gate electrode, a semiconductor pattern, a gate insulating layer, and a first spacer. The first wire pattern is on a substrate and isolated from the substrate. The gate electrode surrounds and intersects the first wire pattern. The semiconductor pattern is on both sides of the first wire pattern, and the semiconductor pattern includes a portion which overlaps the first wire pattern. The gate insulating layer is disposed between the gate electrode and the first wire pattern, and the gate insulating layer surrounds the first wire pattern. The first spacer is between the first wire pattern and the substrate, and the first spacer is between the gate insulating layer and the semiconductor pattern.

Abstract: The present disclosure provides a semiconductor structure includes a substrate and an epitaxy region that is partially disposed in the substrate. A doping concentration of the epitaxy region increases from a bottom portion to a top portion of the epitaxy region. The present disclosure also provides a method for manufacturing the semiconductor structure, including forming a recess in a substrate; forming an epitaxy region in the recess; and in situ doping the epitaxy region to form a doping concentration profile increasing from a bottom portion to a top portion of the epitaxy region.

Abstract: A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.

Abstract: A wiring board includes a first insulating layer made of a single layer of non-photosensitive resin including a reinforcing member, a center position of the reinforcing member being positioned on a side toward a first surface with respect to a center of the first insulating layer in a thickness direction; a layered structure of a wiring layer and an insulating layer, stacked on the first surface of the first insulating layer; a through wiring provided to penetrate the first insulating layer, the through wiring and the first insulating layer forming a first concave portion at a second surface of the first insulating layer, in which the second end surface of the through wiring is exposed; and a pad for external connection formed at the second surface of the first insulating layer at a position corresponding to the through wiring and having a second concave portion.

Abstract: A method of forming an amorphous carbon monolayer (ACM) and an electronic device including the ACM are provided. The method includes forming the ACM on a surface of a germanium (Ge) substrate via a chemical vapor deposition (CVD) process. The CVD process includes injecting a reaction gas including carbon-containing gas and hydrogen (H2) gas in to a reaction chamber containing the Ge substrate, wherein a partial pressure of the H2 gas in the reaction chamber may range from 1 Torr to 30 Torr.

Abstract: A semiconductor device includes; a semiconductor substrate including a major surface; a first diffusion region in the major surface in a main cell region; a second diffusion region in the major surface in a terminal region; an insulating film on the major surface and having first and second contact holes on the first and second diffusion regions respectively; a first electrode in the first contact hole and connected to the first diffusion region; a second electrode in the second contact hole and connected to the second diffusion region; a semi-insulating film covering the second electrode; and a third electrode on the first electrode, wherein the first and second electrodes are made of the same material, the first electrode does not completely fill the first contact hole, the second electrode completely fills the second contact hole, and the third electrode completely fills the first contact hole.

Abstract: A semiconductor structure includes a buffer layer stack comprising a plurality of III-V material layers, and the buffer layer stack includes at least one layered substructure. Each layered substructure comprises a compressive stress inducing structure between a respective first buffer layer and a respective second buffer layer positioned higher in the buffer layer stack than the respective first buffer layer. A lower surface of the respective second buffer layer has a lower Al content than an upper surface of the respective first buffer layer. An active semiconductor layer of the III-V type is provided on the buffer layer stack. The surface of the respective relaxation layers is sufficiently rough to inhibit the relaxation of the respective second buffer layer, and comprises a Root Mean Square (RMS) roughness larger than 1 nm. A method is provided for producing the semiconductor structure.

Abstract: A method for manufacturing a semiconductor device may include the following steps: providing a spacer structure on a first side of a stack structure, wherein the stack structure includes a mask and a conductor; providing an etch stop layer, wherein a portion of the etch stop layer directly contacts both the mask and a portion of the spacer structure; providing a dielectric material member on the etch stop layer; partially removing the first dielectric material member to expose the portion of the etch stop layer; removing the portion of the etch stop layer to expose the portion of the spacer structure; removing the portion of the spacer structure to expose a side of the mask and to form a first spacer; and providing a second spacer, which directly contacts both the first spacer and the side of the mask.

Abstract: A device is disclosed which comprises a first electrode (101), a second electrode (104) spaced from the first electrode, a switching region (102) positioned between the first electrode and the second electrode, and an intermediate region (103) positioned between the switching region and the second electrode, wherein the intermediate region is in electrical contact with the switching region and the second electrode. Preferably, the intermediate region comprises metal nanowires (105) in a polymer matrix, and the device is a memristor or a memcapacitor. In the latter case, the switching region comprises a conductive material (106) and an insulating material (107).

Abstract: A semiconductor device may include a first terminal electrically connected to a first semiconductor chip, a second terminal electrically connected to a second semiconductor chip, which is different from the first semiconductor chip, a first signal line electrically connecting the first terminal and the second terminal and including a first node, a third terminal connected to a tester monitoring a signal transmitted between the first semiconductor chip and the second semiconductor chip, a fourth terminal applied a reference voltage, a second signal line electrically connecting the third terminal and the fourth terminal and including a second node, a first resistor connected between the first node and the second node and a second resistor directly connected to the second node different from the first resistor.

Abstract: Thin film transistors are provided that include a metal oxide active layer with source and drain regions having a reduced resistivity relative to the metal oxide based on doping of the source and drain regions at room temperature. In an aspect, a transistor structure is provided, that includes a substrate, and source and drain regions within a doped active layer having resulted from doping of an active layer comprising metal-oxide and formed on the substrate, wherein the doped active layer was doped at room temperature and without thermal annealing, thereby resulting in a reduction of a resistivity of the source and drain regions of the doped active layer relative to the active layer prior to the doping. In an aspect, the source and drain regions have a resistivity of about 10.0 m?·cm after being doped with stable ions and without subsequent activation of the ions via annealing.

Abstract: An AMOLED back plate includes a substrate on which a buffer layer and a poly-silicon section are sequentially formed. A source and a drain are respectively formed of P-type heavy doped micro silicon on the poly-silicon section that have edges facing and spaced from each other to define a channel therebetween. A gate isolation layer is formed on the buffer layer, the source, the drain and the channel. A gate is formed on the gate isolation layer and has opposite edges that face in directions toward the edges of the source and the drain. The opposite edges of the gate are spaced from the edges of the source and the drain by predetermined spacing distance in horizontal directions so as to prevent the gate from overlapping the source and the drain.

Abstract: A method for manufacturing the thin film transistor, including: forming a gate, an active layer and a gate insulating layer disposed between the gate and the active layer; wherein the gate insulating layer is in a double-layer structure comprising a first gate insulating layer next to the gate and a second gate insulating layer next to the active layer, and one of the first gate insulating layer and the second gate insulating layer is annealed.

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench.

Abstract: Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.

Abstract: An image sensor and a method for forming an image sensor are provided. The image sensor includes a substrate, and the substrate includes a pixel region, a peripheral region and a boundary region, and the boundary region is formed between the pixel region and the peripheral region. The image sensor also includes a first gate stack structure formed in the pixel region and a second gate stack structure formed in the peripheral region. The second gate stack structure includes a high-k dielectric layer and a first metal layer.

Abstract: A liquid crystal panel includes a first substrate, a TFT layer located on the first substrate, a color resist layer located on the TFT layer, a photospacer layer located on the color resist layer, a protective layer located on the color resist layer and the photospacer layer, a via hole penetrating the color resist layer and the protective layer, a pixel electrode layer formed on the protective layer and electrically connected to the TFT layer with the via hole and a second substrate oppositely located to the first substrate, and one or more color resist material in the photospacer layer and the color resist layer are the same, and the photospacer layer and the color resist layer are formed at the same time during a manufacture process.

Abstract: A magnetic junction usable in a magnetic device is described. The magnetic junction includes a first reference layer, first and second spacer layers, a free layer and a self-initializing (SI) substructure. The first spacer layer is between the free and first reference layers. The free layer is switchable between stable magnetic states when a write current having at least a critical magnitude is passed through the magnetic junction. The second spacer layer is between the SI substructure and the free layer. The SI substructure is selected from first, second and third substructures. The first and second substructures include an SI reference layer having a magnetic moment switchable between the first and second directions when a current having a magnitude of not more than one-half of the critical magnitude is passed through the magnetic junction. The third substructure includes a temperature dependent reference layer.

Abstract: Provided are an organic light-emitting display apparatus and a method of manufacturing the same. An organic light-emitting display apparatus includes: a substrate including an active area and a pad area, an anode electrode in the active area, an organic emission layer on the anode electrode, a cathode electrode on the organic emission layer, an auxiliary electrode connected to the cathode electrode, a signal pad in the pad area, and a first pad electrode connected to the signal pad, the first pad electrode covering a top of the signal pad, the first pad electrode being configured to prevent the top of the signal pad from being corroded, wherein the auxiliary electrode includes a first auxiliary electrode and a second auxiliary electrode connected to the first auxiliary electrode through a contact hole, and wherein the first pad electrode includes a same material as the first auxiliary electrode.