Abstract: A level shift amplifier has first to n th inverters connected in series, with each positive voltage terminal of the first to n th inverter is connected to the first source line. Each negative voltage terminal of the first to (n-2)th inverter is connected to output of the second next inverter, respectively. The negative voltage terminal of the (n-1)th inverter is connected to a part of the output of the n th inverter, and the negative voltage terminal of the n th inverter is connected to the second source line. n pieces of feedback elements are connected between the input and output of each inverter. When a feedback element is established so that the gain of each inverter can be maximized, a self-bias amplifier circuit is composed. All inverters are driven by the self-bias voltage. The fine amplitude signals input to the first inverter become the output voltage of full amplitude between the first and second source lines in the n-th inverter.

Abstract: A first substrate (2) carries an array (3) of imaging elements (4). An array (5) of lens elements (6) is provided with each lens element (6) associated with at least one imaging element (4) for concentrating light (L) travelling on a light path between the imaging element (4) and the at least one lens element (6). An electro-optic material (8) having an electrically alterable refractive index is provided in a space defined between a second substrate (7) and one of the imaging element and the lens element arrays (3 and 5). Electrodes (8a,8b) are provided for applying an electrical potential across the electro-optic material (8) to adjust the effective focal length of the lens elements (6). The focal length of the lens elements (6) can thus be adjusted by applying or varying the potential applied across the electro-optic material so that the focus of the imaging device is not entirely dependent on the nature and construction of the lens elements (6 ).

Abstract: A mixed mode buffer circuit 11 including a first input (12), a second input (13), and an output (14). A voltage exceeding a supply voltage of mixed mode buffer circuit 11 can be applied to the output (14) without latchup or an increase in leakage current. The mixed mode buffer includes an output transistor (24) of a first conductivity type having a first electrode coupled to the output (14), a control electrode coupled to the first input (12), a second electrode coupled for receiving the supply voltage, and a bulk electrode. A first transistor (19) biases the bulk electrode when the voltage at the output is within a first predetermined range. A first bulk bias circuit (28) biases the bulk electrode when the output voltage is within a second predetermined range. A second bulk bias circuit (27) and a second transistor (18) couples the voltage at the output to the bulk electrode and the control electrode respectively, when the output voltage exceeds the second predetermined range.

Abstract: A passive broadband sensor protection and enhancement system and technique. ncident light is focused with a cylindrical lens on the optical axis into an intense light strip onto the input face of a photorefractive crystal on the optical axis. The crystal includes optional anti-reflection coatings proximate to the input and output face. A broadband high reflection coating is proximate to the input face for reflection of all radiation from approximately 0.68 to at least out to 1.5 micrometers wavelength. Light exiting from the output face of the crystal results from a photorefractive process that includes a transmitted beam and beam fan. The beam fan is fanned out of the optical path in a direction determined by the c-axis, dominant electro-optic coefficient, and charge carriers participating in the photorefractive process.

Abstract: An electronics circuit for use in determining the position light is incident on a position sensing detector. The position sensing detector provides a pair of photoelectric current signals which indicate the position the light is incident on the detector. These photoelectric current signals are converted to negative ramp voltage signals by a dual switched integrator and then provided through a first pair of sample/hold amplifiers to a second pair of sample/hold amplifiers with each of the second pair of sample/hold amplifiers storing for one line of a raster scan the dark current voltage component of one of the photoelectric current signals.

Abstract: A semiconductor product logic chip (20) including a logic network (27-1) to be fed by a tie-up/tie down circuit (21-1). A tie-up/tie-down circuit is comprised of a non-inverting buffer book (22-1) whose input terminal (23-1) is controlled from the outside by a connection (25) to a primary input terminal (24) of the said chip. Its output terminal (26-1) is connected to said logic network. The primary input terminal is connected to a voltage supply means (29) capable of supplying a constant supply voltage VDD/GND in the SYSTEM mode and a supply voltage varying between VDD and GND, during the TEST mode. When the chip operates in the SYSTEM mode, the supply voltage means is the VDD/GND power supply, so that the primary input terminal is directly tied to the VDD/GND power supply. As a result, the tie-up/tie-down circuit generates a steady logic level "1"/"0" on its output terminal.

Abstract: A clock-generating circuit for logic circuits with clock-controlled decoupling stages includes an interlock circuit which, in an interlocking mode, sets the outputs of the clock-generating circuit and thus, the clock lines, to an interlocking potential, thereby causing the decoupling stages to be placed into a shunt-current-free operating state.

Abstract: Spectral reflection ratios with respect to a second wavelength range are obtained and Fourier transformed to derive frequency converted spectrum. A power spectrum is obtained from the frequency converted spectrum to identify a peak which expresses interference caused by a silicon film. An approximate value d2' of the film thickness of the silicon film is calculated based on the peak position. After filtered by low-pass filtering, the frequency converted spectrum is reverse Fourier transformed to obtain spectral reflectance. From the spectral reflectance, theoretical spectral reflection ratios which are theoretically derived on only one transparent film of the thickness d3 which is formed on a silicon layer are subtracted. An approximate value d1' of the thickness of a silicon oxide film is then calculated from the spectral reflectance which are obtained by subtraction.

Abstract: A signal input circuit having a CMOS inverter for receiving an input signal of a TTL level is disclosed. This circuit includes a first transistor of one channel type connected between a first power terminal and an output terminal and having a gate connected to an input terminal, a second transistor of an opposite channel type connected between a second power terminal and the output terminal and having a gate connected to the input terminal, and a current gain control circuit coupled to the first transistor for controlling the current gain of the first transistor to a first value when a power voltage is at a first level and to a second value when the power voltage is at a second level.

Abstract: A switch matrix including a number of rows of input conductors, a number of columns of output conductors, and switching devices joining selected ones of the input conductors to selected ones of the output conductors, the switching devices being programmable to make connections between input and output conductors, the switching devices joining conductors being positioned on a random basis.

Abstract: A universal logic module for use in a programmable logic device, capable of generating all logical functions of three variables or less. The universal logic module also implements a full adder with carry propagation.

Abstract: A radiation pyrometer for measuring the true temperature of a body is provided by detecting and measuring thermal radiation from the body based on the principle that the effects of angular emission I.sub.1 and reflection I.sub.2 on the polarization states p and s of radiation are complementary such that upon detecting the combined partial polarization state componentsI.sub.p =I.sub.1p +I.sub.2pI.sub.s =I.sub.1s +I.sub.2sand adjusting the intensity of the variable radiation source of the reflected radiation I.sub.2 until the combined partial radiation components I.sub.p and I.sub.s are equal, the effects of emissivity as well as diffusivity of the surface of the body are eliminated, thus obviating the need for any post processing of brightness temperature data.

Abstract: A bias generator circuit provides a bias control signal to the gate of a PMOS transistor which has been added to the inverter which drives the final NMOS pull-down transistor of a CMOS output driver circuit. The bias generator circuit includes a constant current source flowing from the positive supply. The bias generator circuit also includes a current difference circuit containing a resistive divider which drives the gate of an NMOS ballast transistor. This ballast transistor has process/voltage/temperature (PVT) characteristics corresponding to those of the final NMOS pull-down transistor in the CMOS output driver. The channel length of the NMOS ballast transistor and the final NMOS pull-down transistor are drawn the same. The ballast transistor subtracts a PVT adjusted current from the constant current source to produce a PVT adjusted output charging current.

Abstract: A programmable gate array comprises an array of configurable logic blocks. Each configurable logic block is controlled by one or more rows and columns of memory cells in a memory array. According to the invention, an older bitstream may be used without modification in a newer programmable gate array. A frame register includes a plurality of active memory locations called frame bits which correspond to columns of memory cells within the memory array and at least one spare frame bit which does not correspond to a column of memory cells within the memory array. A similar configuration of row pointer cells comprises a shift register for enabling row by row addressing of the memory array.

Abstract: The present invention teaches a touch activated switch. The switch comprises a light source for generating a light ray. Further, the switch comprises a first lens for collimating the light source's light ray. The first lens, as a result, generates a collimated light ray in a first direction. In a second direction, the first lens forms a first and a second focal point, such that the light source is positioned at the first focal point. Moreover, the switch comprises a second lens for converging the collimated light ray to a surface. This surface scatters the collimated light ray in the direction of the first lens when the surface is substantially touched. The switch also comprises a detector for detecting the collimated light ray which have been scattered by touching the surface, with the detector being positioned at the second focal point, such that the switch is activated in response to touching the surface.

Abstract: Voltage translator apparatus to translate TTL or CMOS logic level inputs to 0/-5 V logic levels that is insensitive to temperative and bias supply variation. A unique circuit structure comprises a level shift stage employing transistors configured to level shift a source of operating potential to a controlling potential to be applied to a predriver stage. The controlling potential is a function of the input logic levels. The predriver stage drives an output stage capable of providing complementary 0/-5 V logic outputs. The configuration is such as to afford low power consumption as well as proper operation over wide bias supply and temperature ranges.

Abstract: An integrated circuit output buffer that operates at a low power supply voltage (e.g., 3.3 volts) shares an I/O bondpad with input circuitry that operates at a higher voltage (e.g., 5 volt) signal level. The higher voltage signal level is typically obtained by connection of the bondpad to a bus that is connected to one or more output buffers on other IC's that operate at the higher power supply voltage level. The inventive output buffer obtains a decreased propagation delay by the use of an additional pull-up transistor in a configuration that protects the low voltage output transistors, including the additional transistor, from the higher voltage signal levels present on the bondpad. In this manner, the output buffer may be used in applications that require the relatively low propagation delay specified for the PCI bus, for example.

Abstract: A programmable logic device is disclosed which can be used either as a look-up table logic device or as a logic function generator. This enables combinations to be provided such as the combination of a look-up table with a fixed gate field programmable gate array.