Abstract: A method and an arrangement are provided for generating an estimate of the impulse response of a radio channel. There is generated (202, 406) an initial estimate of the impulse response of a radio channel, and a signal is equalized (203, 407) by using the initial estimate. The equalized signal is decoded (205, 409). There is obtained (411) feedback information from the signal (306) after equalization, an updated channel estimate is generated (304 412) by using said feedback information, and the signal is equalized (407) again by using said updated channel estimate and said feedback information.

Abstract: A method and apparatus for estimating channels in orthogonal frequency division multiplexed (OFDM) communication systems. The method and apparatus allows a channel estimate to be determined independent of having knowledge on channel statistics. Channel estimation is performed by determining and then utilizing a least square (LS) estimate and an interpolation coefficient for each antenna transmitting to the receiver. The interpolation coefficient is determined independently from the statistics of the channel, i.e., without needing the channel multipath power profile (CMPP). The interpolator coefficient is multiplyed by an LS estimate for each transmitting antenna to determine the channel estimate for each channel.

Abstract: A channel estimation method which reduces the strain on resources of a Rake receiver using a complex weight gain (CWG) algorithm. In one embodiment, a non-adaptive algorithm is used to average blocks of pilot symbols from several slots. In another embodiment, an adaptive algorithm implements sliding window averaging or a recursive filter. Using a CWG algorithm reduces the memory and processor requirements of the Rake receiver.

Abstract: A non-uniform filter bank is created by joining sections of oversampled uniform filter bands that are based on complex exponential modulation (as opposed to cosine modulation). Each filter bank handles a given, non-overlapping frequency band. The bands are not of uniform bandwidth, and the filters of different banks have different bandwidths. The frequency bands of the different filter banks cover the frequency of interest with gaps in the neighborhoods of the filter band edges. A set of transition filters fills those gaps.

Abstract: A method for reducing interference within a communication system is provided herein. A receiver (100), and method for operating a receiver are provided. The receiver operates by utilizing a filter bank (103–104) to partition a wide-band signal into smaller sub-bands. Interference suppression takes place individually on the sub-bands (frequency bands) instead of on the wideband signal as a whole. By using interference suppression on smaller sub-bands, interference suppression techniques can be utilized with less computational complexity than when performing interference suppression on the broadband signal as a whole.

Abstract: A clock recovery circuit and a method for reducing electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers said modulated clock frequency signed to generated an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector.

Abstract: A method and apparatus for accurately estimating the carrier frequency offset and the carrier phase offset of a digitally modulated signal using a signal processing algorithm to initialize the state variables of a Phase-Locked Loop (PLL) is disclosed. A sequence of phase values is estimated from a received sequence of symbols and the angular effect due to the modulation format is removed from the sequence of phase values. A curve-fit algorithm based in one embodiment on the RLS algorithm is then applied to a sequence of unwrapped phase values to estimate the carrier frequency offset and the carrier phase offset.

Abstract: In a method for adaptive synchronization of a data sink device to a data source device coupled by a USB, data is received and stored in a buffer of the sink device at an average data rate representative of the data rate of the source device. A data level for the buffer is determined based on input packet size and output packet size. An accumulated data level for the buffer is compared with a threshold level. A clock frequency for the sink device is corrected when the accumulated data level exceeds the threshold level.

Abstract: A system for detecting a burst in a wireless communications system. A signal strength indicator indicates the strength of an incoming signal representative of incoming packets. A signal strength change detector detects changes in the signal strength of the incoming signal. Signal strength detection logic determines if a change in signal strength of a predetermined magnitude has occurred. A pattern detector detects patterns of symbols, or symbol estimates, in the incoming signal to determine if a predetermined pattern of symbols is present. Burst detection logic signals detection of a burst if the signal strength detection logic determines that a change in signal strength of predetermined magnitude has occurred, and the pattern detector determines that a predetermined pattern of symbols is present.

Abstract: A method and an arrangement for determining correction parameters used for correcting DC-offset of an I/Q modulator in a transmitter comprising an I/Q modulator and a corrector for correcting the DC-offset caused by the I/Q modulator are presented. The method comprises sampling the I/Q-modulated test signals, which are formed from I/Q-plane test vectors, A/D-converting the signal samples taken from the test signals, I/Q-demodulating the signal samples digitally into I- and Q-feedback signals, determining the DC-offset caused by the I/Q modulator on the basis of the test vectors and the feedback vectors caused by the test vectors and formed from the I- and Q-feedback signals, and determining the correction parameters of DC-offset on the basis of the determined DC-offset.

Abstract: A method for synchronizing a data signal and a clock signal has been developed. The method first generates two separate intermediate data signals. The intermediate data signals lag the input data signal. The separate durations of the two lagging signals are combined to form an output data signal that is synchronized with the system clock signal.

Abstract: Fractional bit rate encoding in a pulse amplitude modulation (PAM) communication environment allows the transmission of fractional bit rates, thus maximizing the use of signal-to-noise ratio (SNR) available on a communication channel. The invention allows the transmission of fractional bit rates in a PAM transceiver, thus allowing the encoding and transmission of a fractional number of bits on each PAM transmit symbol. By encoding a non-integer number of bits, a non power-of-two number of PAM levels can be encoded.

Abstract: A receiver architecture featuring a decimation filter and a bypass around said decimation filter is disclosed along with a method for optimizing said receiver's sampling phase and programmable gain amplifier. Said method utilizes said receiver architecture to modify said receiver's receive path to simplify optimizations.

Abstract: Phase selection mechanisms for the optimal sampling of data at the receiving end of a SSC interface. The receiver is allowed to choose between several phases of its local clock, to best synchronize the transmitter data to the receiver clock domain. It results in a minimum depth first in first out (FIFO) register to accomplish the handoff of transmit data from the transmit clock to the receive dock. It avoids the requirement of a delay locked loop (DLL) to bring the transmitter clock into a desired phase relationship with respect to the receiver clock. At least one embodiment of the present invention provides a solution specific to the DDR or full rate clocking SSC interface.

Abstract: A scalable clock recovery system. In one embodiment the system comprises a clock master unit, a clock distribution network, and a plurality of clock recovery units. The master clock unit generates a plurality of master clock signals, which are received by the clock recovery units. The clock recovery units use multiple stages of mixing to generate a recovered clock. The recovered clock can be used to recover data from a serial data stream.

Abstract: The invention relates notably to a method for modulating information symbols to be transmitted in a CDMA communication network by using a non-orthogonal modulation code comprising M spreading sequences (sm 1?m?M), each comprising in N chips (sm,n 1?n?N), the M spreading sequences having the same energy. According to the invention, the amplitude of the chips take a plurality of values the number M of spreading sequences is higher than the number of chips N per spreading sequence.

Abstract: The present invention is a method of acquiring phase lock to a data signal in a digital channel having a digital feedback loop. The method generally comprises: (A) applying the data signal to an analog phase lock loop configured to have (i) at least two poles and (ii) presend intermediate output signal frequency locked to the data signal; (B) applying the data signal and the intermediate output signal to the digital channel; and (C) adjusting a delay constant for the digital feedback loop to (i) compensate for variations in phase between the data signal and the intermediate output signal and (ii) acquire phase lock by using a single pole in the digital channel.

Abstract: A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a voice exchange, a data exchange and a call discriminator. The voice exchange is capable of exchanging voice signals between a switched circuit network and a packet based network. The signal processing system also includes a data exchange capable of exchanging data signals modulated by a voiceband carrier on the switched circuit network with unmodulated data signal packets on the packet based network. The data exchange is performed by demodulating data signals from the switched circuit network for transmission on the packet based network, and modulating data signal packets from the packet based network for transmission on the switched circuit network. The call discriminator is used to selectively enable the voice exchange and data exchange.

Abstract: A process is proposed for recovering disturbed digital signals, wherein the electrical signals pass through a feedback equalizer and an analogue control of the setting parameters of the equalizers is performed. A pseudo-error monitor, which facilitates a high-speed adjustment of decision element thresholds, is also provided.

Abstract: A method and system is provided for clock/data recovery for self-clocked high speed interconnects. A data signal is received and then equalized. The equalized data signal then provides the trigger to separate “ones” and “zeros” one-shots. The equalized Manchester data signal is also integrated, compared with a threshold value to determine the negative and positive peaks of the data signal. Then after the appropriate peak is determined, a mid-bit signal is sent as input to a set-reset flip-flop which thereby outputs an asynchronous recovered non-return to zero signal. This asynchronous recovered non-return to zero signal then provides an enable input to the “ones” one-shot and the complementary asynchronous recovered non-return to zero signal provides an enable input to the “zeros” one-shot. The “ones” one-shot outputs a “ones” clock signal and the “zeros” one-shot outputs a “zeros” clock signal. These two signals are verified and a recovered clock out signal is provided.