Patents Examined by Stephen D Berman
  • Patent number: 10324741
    Abstract: According to one technique, a virtual machine stores type profiling data for program code, the type profiling data indicating observed types for profiled values within the program code at specific profile points during previous executions of the program code. The virtual machine determines to optimize a particular code segment of the program code. The virtual machine generates a program representation describing a flow of data through different variables within the code segment. The virtual machine assigns speculative types to certain variables in the particular code segment by: assigning speculative types of first variables to respective observed types recorded in the type profiling data; calculating speculative types of second variables, based on propagating the speculative types of the first variables through the program representation.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: June 18, 2019
    Assignee: Oracle International Corporation
    Inventors: Roland Westrelin, John Robert Rose
  • Patent number: 10318283
    Abstract: Managing sets of parameter values includes: receiving a plurality of sets of parameter values for a generic computer program, and processing log entries associated with executions of instances of the generic computer program, each instance associated with one or more parameter values. The processing includes: analyzing the generic computer program to classify each of one or more parameters associated with the generic computer program as a member of either a first class or a second class; processing a log entry associated with an execution of a first instance of the generic computer program to form a particular set of parameter values; and determining whether to add the particular set of parameter values to the plurality of sets of parameter values based on a comparison of a first identifier for the particular set of parameter values to identifiers for at least some of the sets of parameter values.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: June 11, 2019
    Assignee: Ab Initio Technology LLC
    Inventors: Edward Bach, Richard Oberdorf, Brond Larson
  • Patent number: 10289399
    Abstract: In one example of the present disclosure, a computing system is provided. The computing system is to initiate a power on self-test (POST) process, determine that a change has been made to system firmware configuration data, start a timer, and determine that the timer has expired. Thereafter, the computing system is to power-off and power-on the computing system, replace current system firmware configuration data with backup system firmware configuration data, and/or generate a notification indicating system firmware configuration data has been reverted.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: May 14, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Christopher H Ham, Scott B Marcak
  • Patent number: 10261764
    Abstract: In one approach, a method comprises receiving one or more higher-level instructions specifying to assign a value of a particular value type to a particular container of a plurality of containers, wherein the plurality of containers represent a data structure for maintaining one or more variables during execution of a block of code, wherein at least two containers of the plurality of containers are different sizes; generating one or more lower-level instructions that assign the value to the particular container based on applying one or more assignment rules to the one or more higher-level instructions based on the particular value type and executing the one or more lower-level instructions.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: April 16, 2019
    Assignee: Oracle International Corporation
    Inventors: John Robert Rose, Brian Goetz, Guy Steele
  • Patent number: 10255166
    Abstract: A method to determine a valid input sequence for an unknown binary program is provided. The method may include obtaining an input sequence for an unknown binary program. The method may also include obtaining a memory address range for each of one or more variables in the unknown binary program and executing an instrumented version of the unknown binary program with the input sequence as an input to the instrumented version of the unknown binary program. The method may also include recording one or more memory addresses accessed during the execution of the instrumented version of the unknown binary program and determining that the unknown binary program accepts the input sequence as valid based on one or more of the one or more recorded memory addresses corresponding to the memory address range of one or more of the variables in the unknown binary program.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: April 9, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Praveen Murthy, Bogdan Copos
  • Patent number: 10235266
    Abstract: Disclosed herein are methods that include receiving application source code of a mobile application, analyzing the application source code to generate screen metadata that represents screen images that will be generated by the mobile application upon execution of binary application code generated from the application source code, storing the screen metadata in a screen metadata file, and associating the screen metadata file with the mobile application.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: March 19, 2019
    Assignee: CA, Inc.
    Inventor: Seshadri Venkataraman
  • Patent number: 10235265
    Abstract: System and method for validating a program under a specified model of computation. The model of computation may be related to the synchronous statechart model of computation. A program may be received that specifies a plurality of operations using a variable within a logical tick such that the variable has multiple values within the logical tick. The program may be statically analyzed according to a specified model of computation that specifies program execution based on logical ticks, which may include determining that the program has deterministic semantics that specify deterministic results for each logical tick during execution of the program, including specifying deterministic results of the plurality of operations performed within the logical tick. The program may be validated in accordance with the specified model of computation in response to the determining.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: March 19, 2019
    Assignee: National Instruments Corporation
    Inventors: Reinhard von Hanxleden, Michael Mendler, Stephen R. Mercer, Owen B. O'Brien
  • Patent number: 10198252
    Abstract: The splitting of an application in response to detected environmental events (such as user input). Such splitting may be performed for purposes of sharing the application. The application is a transformation chain instance. From the detected environmental event(s), it is determined that a portion transformation chain class is to be created from the larger transformation chain class of the application. In response, the portion transformation chain class is created, instantiated and operated. A sharing mechanism may be used to allow the split portion of the application to be shared with other entities without losing control.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: February 5, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Vijay Mital, Robin Abraham, Henry Hun-Li Reid Pan, Sandeep Suresh, Bao Quoc Nguyen, George Edward Busby, Curtis DeSantis
  • Patent number: 10198251
    Abstract: Examples described herein emulate a processing architecture using multiple translations of the same source binary. A first translation binary includes compiler optimizations not present in a second translation binary. During runtime, a dispatcher directs control flow of a CPU when branch instructions are reached. Specifically, a dispatcher directs a CPU to execute instructions in the first translation binary, and accesses the second translation binary when an instruction is to a target that is not addressable in the first translation binary. The first and second translation binaries enable a target processing architecture to emulate a source processing architecture without just-in-time compilation or other runtime interpretation.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: February 5, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Henry Paul Morgan
  • Patent number: 10185573
    Abstract: An image of system software is installed by loading an executable image of the system software using a boot loader, where the executable image includes a kernel and a plurality of files used by the kernel. The kernel of the system software is executed to generate the image of the system software that includes a copy of the kernel. Generating the image of the system software involves the steps of generating a plurality of pointers that each point to a different one of the files, retrieving the files using the pointers, and storing a copy of the kernel and the files in a storage device from which the system software is to be booted as the image of the system software.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: January 22, 2019
    Assignee: VMWARE, INC.
    Inventors: Daniel K. Hiltgen, Olivier A. Cremel, Christopher P. Devine
  • Patent number: 10175964
    Abstract: A compiler-created cache contains target addresses of multiple indirect routine call sites. Ordinals assigned to indirect routine call sites are used with hardcoded offsets into the cache. Ordinals may be computed using a routine counter and an indirect call site counter. At runtime a target address of an indirect routine call site is compared to an entry in the cache using the hardcoded offset for efficiency. If the target address matches the cache entry, then a redundant call is avoided; otherwise, the call is not redundant, and the cache is updated. The call tested for redundancy may be a security check for malware, or a computationally expensive routine which calculates a return value without any side effects. Stack pointer validity may be checked. The cache may be guarded with code for trustworthy computing. Tail merging may be performed.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: January 8, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: James J. Radigan
  • Patent number: 10140112
    Abstract: In an update management system including a plurality of servers executing a communication service, a server not connected to a network in which a new version of an application is operated is generated in parallel with a server in which an old version of the application is operated, and old and new correspondence data between an old version server and a new version server is generated and used to execute switching from the old version server to the new version server in a flow on the network and to execute switching-back to the old version server by referring to the old and new correspondence data at the time of occurrence of fault in a new version.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: November 27, 2018
    Assignee: NTT DOCOMO, INC.
    Inventors: Yusuke Takano, Takashi Shimizu, Motoshi Tamura, Hidenori Asaba, Takeo Yamasaki, Masaaki Kosugi
  • Patent number: 10095488
    Abstract: Various of the disclosed embodiments concern systems and methods for constructing enterprise applications. A universal Smart Enterprise Information platform can operate as a hub for data retrieved from different internal and external sources and provide an integrated and automated way for enterprise information to be managed. More specifically, the platform is able to retrieve data from one or more sources and construct models that represent, for example, common business scenarios. The platform employs assorted software development techniques to bring together the business, design, and runtime domains. Using a unique development paradigm (“CORTEX”), the models can be used to construct an application with minimal programming efforts.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: October 9, 2018
    Assignee: BRAINTRIBE IT—TECHNOLOGIES GMBH
    Inventors: Stefan Ebner, Peter Brandner, Peter C. Steinlin, Dirk Scheffler, Gunther G. Schenk
  • Patent number: 9921865
    Abstract: A system and method for system table modification in a virtualized computer system are disclosed. In accordance with one embodiment, a hypervisor that is executed by a computer system detects an attempt by a guest operating system of a virtual machine to access a system table. In response to the detecting, the hypervisor determines a hardware configuration of the virtual machine, and populates one or more entries of the system table in view of the hardware configuration.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: March 20, 2018
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Gerd Hoffman