Patents Examined by Stephen D. Meies
  • Patent number: 5176366
    Abstract: A semiconductor device in which outer leads adjoining in the direction of arrangement of said outer leads are connected by an insulating material with a predetermined width, locally provided only in the areas with said predetermined width along said direction of arrangement, and in which areas other than said outer leads and said insulating material are resin-sealed. A method for manufacturing a semiconductor device, which has the steps of connecting adjacent outer leads, with an insulating material with a predetermined width locally provided only in areas with said predetermined width along the direction of arrangement of outer leads, and of resin-sealing areas other than said outer leads and said insulating material while preventing the outflow of sealing resin by way of said insulating material.
    Type: Grant
    Filed: October 4, 1990
    Date of Patent: January 5, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Kenji Masumoto, Takashi Nakashima