Abstract: The gate electrodes of the driver MISFETs, transfer MISFETs and load MISFETS of the static random access memory (SRAM) are formed of the first-level conductive layer deposited over the main surface of the semiconductor substrate. The gate electrodes, power source voltage line, reference voltage line, local interconnection lines, and complementary data lines, all making up the conductive layers of the SRAM memory cell, are formed of different conductive layers, i.e. conductive layers of different levels. The local interconnection lines and the reference voltage line or power source voltage line are arranged, with respect to a plan view of the main surface of the substrate, to cross each other and a capacitance is formed in the intersecting regions.

Abstract: It is possible to limit the voltage across a diode to the level of the pinch-off voltage of a JFET in an integrated circuit by connecting the diode in series with the JFET. As a result, the voltage offered through the JFET can be higher than the breakdown voltage of the diode, which is of particular importance in high-voltage ICs in which a highly doped buried zone is formed below the diode for reducing leakage currents to the substrate. According to the invention, the JFET together with at least one further circuit element is formed in a common island surrounded by an island insulation region. The gate of the JFET extends along the edge of the island and is separated from the relevant portion of the island insulation region substantially only by the source of the JFET. In the pinch-off condition, the gate divides the island into a high-voltage portion and a low-voltage portion which is coupled to the diode.

Abstract: A field effect semiconductor device having multiple vertically stacked channels (12, 14, 16) separated by barrier layers comprising wide bandgap material (18) is provided. The channels (12, 14, 16) are formed on a wide bandgap buffer layer (11) and each channel is coupled a P-type drain region (22b). Each channel is also coupled to an N-type source region (25b). With appropriate gate bias on a gate electrode (17), quantized energy levels in the channels (12, 14, 16) are aligned providing peak current flow by electrons tunneling from the conduction band of one or more N-channels (12, 16) to the valence band of the P-channel (14).

Abstract: A nonvolatile semiconductor memory has active regions that form parallel strips extending in a first direction in a semiconductor substrate. Each active region has source areas, drain areas, and channel areas for a series of memory cells. Floating gates are formed over the channel areas, and control gates over the floating gates. The upper surfaces of the control gates and the sides of the control gates and floating gates are covered by insulating films. Source interconnecting lines made of a conductive material are formed as parallel strips extending in a second direction different from the first direction on the semiconductor substrate, interconnecting the source areas of the memory cells.

Abstract: An integrated circuit device has a substrate, a plurality of circuit elements or units arranged on the substrate and having terminals, a plurality of signal lines connected between the terminals of the circuit elements or units, or between the terminals and external connection terminals, and an alternating current ground line provided close to the signal lines to determine a transmission characteristic of the signal lines, the alternating current ground line including a high-potential direct current power source line and a low-potential direct current power source line, the high-potential direct current power source line and the low-potential direct current power source line being vertically separated by a dielectric layer.

Abstract: Disclosed is a Dynamic Random Access Memory (DRAM) cell which includes a storage capacitor disposed in a trench formed in a semiconductor substrate and an access transistor disposed in a well which is opposite in conductivity type to that of the substrate and a buried oxide collar which surrounds an upper portion of the trench.