Abstract: A computationally implemented system and method that is designed to, but is not limited to: electronically receiving one or more communication network relay related transmissions at least in part associated with one or more first portions of mobile operating system operated intermediate electronic communication device functionality related at least in part to communication network relay functionality of a mobile operating system operated intermediate electronic communication device as one or more standby communication network relays upon activation thereof for use by one or more origination electronic communication devices to communicate at least in part with one or more destination electronic communication devices, the mobile operating system operated intermediate electronic communication device functionality including second portions related at least in part to mobile electronic communication device functionality.

Abstract: Methods and apparatus for restricting access by one or more processors to an area of a secondary storage unit are presented herein. The methods and apparatus may comprise an independent programmable storage controller logic that divides a storage area of the secondary storage unit into at least a first area and a second area and controls usage of the areas as at least two virtual secondary storage units such that the processor(s) access the at least two virtual secondary storage units as if accessing at least two physical secondary storage units by selecting one of the at least two virtual secondary storage units as an active virtual secondary storage unit to provide the processor(s) access to the active virtual secondary storage unit based on a secondary storage unit configuration. Each virtual secondary storage unit may contain at least one region of which an access permission setting is modifiable.

Abstract: A system and method for managing cache replacements and a memory subsystem incorporating the system or the method. In one embodiment, the system includes: (1) a cache controller operable to control a cache and, in order: (1a) issue a pre-fetch command when the cache has a cache miss, (1b) perform at least one housekeeping task to ensure that the cache can store a replacement line and (1c) issue a fetch command and (2) a memory controller associated with a memory of a lower level than the cache and operable to respond to the pre-fetch command by performing at least one housekeeping task to ensure that the memory can provide the replacement line and respond to the fetch command by providing the replacement line.

Abstract: A method and system for dynamic distributed data caching is presented. The system includes one or more peer members and a master member. The master member and the one or more peer members form cache community for data storage. The master member is operable to select one of the one or more peer members to become a new master member. The master member is operable to update a peer list for the cache community by removing itself from the peer list. The master member is operable to send a nominate master message and an updated peer list to a peer member selected by the master member to become the new master member.

Abstract: A plurality of storage nodes in a single chassis is provided. Each of the plurality of storage nodes has a storage capacity with nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to support uniform storage capacities and non-uniform storage capacities among the plurality of storage nodes, as a storage cluster. The plurality of storage nodes is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can read the user data, using erasure coding, despite loss of two of the plurality of storage nodes.

Abstract: A memory cell programming method for a rewritable non-volatile memory module is provided. The method includes grouping physical erasing units of the rewritable non-volatile memory module at least into a first area and a second area, wherein a first programming parameter set is configured initially for writing a first kind of data into the physical erasing units of the first area and the upper physical programming units of the physical erasing units of the first area are not written with data. The method also includes adjusting the first set of programming parameters to obtain a second programming parameter set, and applying the second set of programming parameters to write a second kind of data into the physical erasing units of the second area, wherein the upper physical programming units of the physical erasing units of the second area are not written with data.

Abstract: A storage system is provided. The storage system includes a plurality of storage units, each of the plurality of storage units having storage memory for user data and a plurality of storage nodes, each of the plurality of storage nodes configured to have ownership of a portion of the user data. The storage system includes a first pathway, coupling the plurality of storage units such that each of the plurality of storage units can communicate with at least one other of the plurality of storage units via the first pathway without assistance from the plurality of storage nodes.

Abstract: Ascertaining command completion in flash memories is disclosed. An exemplary aspect includes eliminating the software lock and the outstanding requests variable and replacing them with a transfer request completion register. The transfer request completion register may be mapped to the universal flash storage (UFS) Transfer Protocol (UTP) Transfer Request List (UTRL) slots. The controller of the host—a hardware component—may set the bit in the transfer request completion register on transfer request completion at the same time the doorbell register is cleared. After this bit has been read, the bit in the transfer request completion register is cleared.

Abstract: An apparatus comprising an interface and a control circuit. The interface may be configured to process a plurality of read/write operations to/from a memory. The control circuit may be configured to determine if a read disturb has occurred. If the read disturb has occurred, the control circuit may (a) determine a size of a group of the read/write operations and (b) write all of the group of the read/write operations to one of a plurality of memory modules of the memory.

Abstract: A mechanism is provided in a cache subsystem for cache prefetching based on non-sequential access. The mechanism determines frequently accessed non-sequential cache records in the cache subsystem. The mechanism collects trailing record statistics for the frequently accessed non-sequential cache records. The mechanism determines a caching strategy. The caching strategy comprises prefetching a set of trailing records responsive to a read of a given frequently accessed non-sequential cache record. The mechanism applies the caching strategy to the cache subsystem.

Abstract: The present application provides an improved approach for managing performance tier de-duplication in a virtualization environment. A content cache is implemented on high performance tiers of storage in order to maintain a working set for the user virtual machines accessing the system, and associates fingerprints with data stored therein. During write requests from the user virtual machines, fingerprints are calculated for the data to be written. However, no de-duplication is performed during the write. During read requests, fingerprints corresponding to the data to be read are retrieved and matched with the fingerprints associated with the data in the content cache. Thus, while multiple pieces of data having the same fingerprints may be written to the lower performance tiers of storage, only one of those pieces of data having that fingerprint will be stored in the content cache for fulfilling read requests.

Abstract: Various systems, methods, apparatuses, and computer-readable media for accessing a storage device are described. In certain example embodiments, an active/active fault tolerant storage device comprising two or more controllers may be implemented. In one embodiment, each controller may be coupled to the non-volatile memory (NVM) blades comprising the non-volatile memory (NVM) storage medium. In one example implementation, a standardized protocol, such as Peripheral Component Interconnect Express protocol may be used for communicating amongst the various components of the controller and also the NVM storage medium.

Abstract: A memory system and method for improving read latency of a high-priority partition are provided. In one embodiment, a memory system receives a command to store data in the memory. The memory system determines if the command specified that the data is to be stored in a standard partition in the memory or in a high-priority partition in the memory. If the command specified that the data is to be stored in a standard partition in the memory, the memory system stores the data using a first write technique. If the command specified that the data is to be stored in a high-priority partition in the memory, the memory system stores the data using a second write technique, wherein the second write technique provides improved read latency of the stored data. Other embodiments are disclosed.

Abstract: A computer-executable method, system, and computer program product for managing a data storage system, wherein the data storage system includes a cache and a data storage array, the computer-executable method, system, and computer program product comprising receiving initialization information, analyzing the initialization information to determine which portions of the data storage array related to the initialization information, and managing the data storage system based on the determined portion of the data storage array.

Abstract: An interconnect has transaction tracking circuitry for enforcing ordering of a set of data access transactions so that they are issued to slave devices in an order in which they are received from master devices. The transaction tracking circuitry is reused for also enforcing ordering of snoop transactions which are triggered by the set of data access transactions, for snooping master devices identified by a snoop filter as holding cache data for the target address of the transactions.

Abstract: A method and apparatus configured to restore a flash translation layer (“FTL”) in a non-volatile (“NV”) storage device are disclosed. After reactivating the NV storage device from an unintended system crash, a process of recovering FTL, in one embodiment, receives a request for restoring at least a portion of the FTL or FTL database. After identifying sequence numbers (“SNs”) associated with flash memory blocks (“FMBs”) which are generated during write cycle(s), the SNs are retrieved from the information storage locations such as state information in the FMBs. A portion of the FTL database is subsequently reconstructed in a random access memory (“RAM”) according to the SNs. In an alternative embodiment, logical block addresses (“LBAs”), LBA lists, and/or index tables can also be used to restore the FTL database or table.

Abstract: A method for memory utilization by an electronic device is described. The method includes transferring a first portion of a first decision tree and a second portion of a second decision tree from a first memory to a cache memory. The first portion and second portion of each decision tree are stored contiguously in the first memory. The first decision tree and second decision tree are each associated with a different feature of an object detection algorithm. The method also includes reducing cache misses by traversing the first portion of the first decision tree and the second portion of the second decision tree in the cache memory based on an order of execution of the object detection algorithm.

Abstract: A computer-executable method, system, and computer program product of managing a data storage system, wherein the data storage system includes a cache and a data storage array, the computer-executable method, system, and computer program product comprising initializing the cache, wherein the initializing comprises creating a first list related to data stored on the cache, and creating a second list related to data stored on the data storage array, updating the first list based on received I/O requests, updating the second list based on received I/O requests, and managing data on the cache based on the first list and the second list.

Abstract: A data management method is provided. The method includes: dividing each of physical programming units into a data bits area and a spare bits area; generating first data management information corresponding to first data according to a first write command and the first data; determining whether the first data is compressible; and generating first data compression information corresponding to the first data. The method further includes: if the first data is compressible, compressing the first data to generate first compressed data, programming the first compressed data and the first data management information corresponding to the first data into a first data bits area of a first physical programming unit among the physical programming units, and programming the first data compression information into the first spare bits area of the first physical programming unit.

Abstract: A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.