Patents Examined by Stephen Jackson
  • Patent number: 6965502
    Abstract: The present invention provides a power regulation system and method with high speed signal settling capabilities for providing rapid active transient response to a microelectronic device. An active transient response system includes a power supply configured to receive external and/or internal signals indicating the occurrence of transient load conditions and to respond to the transient load conditions based on one or more of these signals. The system may further include a transient suppressor configured for early detection of transients, assisting in transient suppression, and early signaling of transient activity to the power supply. The system provides rapid recovery to steady state operation from the active transient response mode by using a digital compensator to quickly modifying the duty cycle and provide a voltage offset proportional to the transient microprocessor load step. Recovery is further improved by current rephasing techniques.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: November 15, 2005
    Assignee: Primarion, Inc.
    Inventors: Thomas P. Duffy, Ryan Goodfellow, Malay Trivedi, Kevin Mori, Benjamim Tang
  • Patent number: 6157529
    Abstract: The specification discloses a Basic Surge Protector for protecting an electrical equipment connected on its load side from spurious or excessive transient voltages or surges or both on an electrical line above a predetermined value, on its line side or its hot side. Intended for use in ac circuits, dc circuits and ac/dc circuits. A fuse is used to monitor a fault current flowing into a surge voltage suppression device, due to an excessive voltage across the suppression device. Thus the fuse blows resulting from an over-current condition, and it disables and opens a solid state switch or an electro mechanical switch mounted in series in the line thus protecting the secondary or the load side from over-voltages and transient surges on the electrical line. Circuits are also disclosed which provide for automatic setting and resetting after an over-voltage fault condition on the line being protected.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: December 5, 2000
    Inventor: Om Ahuja
  • Patent number: 6091597
    Abstract: An improved structure of an electric shock device includes a handle, and a plurality of retractable rod portions. The handle has an interior accommodating therein a high voltage generator and a battery unit. The handle further has a control switch at a lower rim thereof. The retractable rod portions are arranged and assembled in order of size, and equipped with a retractable function by utilizing springs and retaining rods disposed therein. The rod portions are made of insulating materials and respectively provided with parallel positive and negative electrode plates on both sides thereof. The electrode plates nearest to the handle are connected to positive and negative terminals of the high voltage generator so as to supply the rod portions with the required high voltages. The permittivity of dielectrics on the rod portions that have different diameters is caused to be equivalent so that the conductance conditions of the rod portions are the same, and the rod portions can all generate electric arcs.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: July 18, 2000
    Inventor: Ming-Chen Lin
  • Patent number: 6043969
    Abstract: Electrostatic discharge (ESD) protection is provided for NMOS pull up transistors 700A-H and 702A-H of a 5.0 volt compatible output buffer using 2.5 volt process transistors. The ESD protection includes ballast resistors 701A-H and 703A-H separating individual pairs of NMOS pull up transistors 700A-H and 702A-H from the pad and from a power supply connection NV3. The ballast resistors enable turn on of additional pairs of NMOS pull up transistors after a first pair, such as 700A,702A turns on during an ESD event to prevent secondary breakdown in the first NMOS pair. Pairs of NMOS pull up transistors are used to prevent voltages across individual NMOS transistors from exceeding a 2.7 volt maximum while still enabling the transistors to provide 5.0 volts to the pad.
    Type: Grant
    Filed: July 13, 1998
    Date of Patent: March 28, 2000
    Assignee: Vantis Corporation
    Inventor: Bradley A. Sharpe-Geisler
  • Patent number: 6043965
    Abstract: A circuit having reverse battery protection includes a combination of an electrical load and an N-channel MOSFET inversely coupled in series with the load. The gate of the MOSFET is coupled to the high potential side of the electrical load. The series combination is powered by a DC voltage source. Positive polarity voltages enhance the MOSFET and provide for low loss conduction thus completing the series circuit whereas negative polarity voltages bias the MOSFET off thus providing a DC block by way of the intrinsic diode of the inversely coupled MOSFET. Gate to source voltage may be limited or controlled to prevent damage due to punch through effects at high positive voltages and to ensure turn-off of the MOSFET at negative polarity voltages.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: March 28, 2000
    Assignee: General Motors Corporation
    Inventors: Lawrence Dean Hazelton, Lance Ronald Strayer
  • Patent number: 6021034
    Abstract: A ground fault protection circuit for plural loads connected across a power source with plural branches which can be used where the loads are unbalanced. Each branch includes a ground fault circuit interrupter device that has a common line for the electronics of the GFCI separate from the neutral line from the power source to the load where the common lines for the electronics for the ground circuit interrupter devices in each branch are connected to a common point. The ground fault protection circuit employs plural ground fault circuit interrupter devices and eliminates nuisance tripping. The common line for the electronics for a GFCI is routed through the core of the current sensing transformer of the GFCI. The separate neutral line for the electronics, connecting the common lines for the electronics for plural GFCI devices and routing the common lines for the GFCI electronics through the core of the transformer of each GFCI, eliminate improper GFCI operation due to unbalanced loading.
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: February 1, 2000
    Assignee: Leviton Manufacturing Co., Inc.
    Inventors: David Chan, Paul Gernhardt
  • Patent number: 6014297
    Abstract: A multiwire branch circuit including two line conductors and a grounded, common neutral conductor is protected by a two pole circuit breaker connected to independently interrupt overcurrent conditions in the two ungrounded line conductors. Three separate protection circuits provide arc fault protection for each of the ungrounded line conductors and ground fault protection for all three conductors. The arc fault detectors use the bimetal of the thermal-magnetic trip device for the associated line conductor for current detection, and therefore, are individually referenced to the associated line voltage. Hence, the outputs of the arc fault detectors are electrically isolated from each other and from the output of the ground fault detector, but operate a common trip circuit to simultaneously open both poles of the two pole circuit breaker. The arc fault detectors have separate isolated power supplies.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: January 11, 2000
    Assignee: Eaton Corporation
    Inventors: Robert J. Clarey, Richard P. Sabol, Robert Tracy Elms
  • Patent number: 6014300
    Abstract: A power source circuit includes switch for connecting and disconnecting a power source to and from a circuit proper; stabilizing means for suppressing a variation of an input voltage to stabilize the input voltage; voltage increasing means for increasing the input voltage in amplitude; switching means for controlling a voltage increasing operation; rectifying means for rectifying a switching waveform; smoothing means for smoothing a rectified waveform; and control means for controlling an output voltage to be constant in amplitude. In the power source circuit, the start of operating the power source circuit is delayed behind the start of supplying electric power. Therefore, it is prevent a power source circuit from failing to operate under the condition that a power source of a large internal resistance is coupled thereto, and the rush current, for example, causes the power source voltage drop.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: January 11, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Koichi Yamashita, Hiroaki Sugiura, Tetsuya Kuno, Narihiro Matoba
  • Patent number: 6002569
    Abstract: Apparatus for protecting at least one internal component of a printed circuit board provided inside a housing from an electrostatic discharge which is generated from outside the housing and enters through an external component to which the at least one internal component is connected, includes a base imbedded between a resist layer and a substrate of the printed circuit board to electrically ground the electrostatic discharge. A node is provided between the external component and the at least one internal component to be protected, for shunting the electrostatic discharge away from the internal component and to the base. Also included is a mask provided in a space between the base and the node for maintaining an electrical disconnection between the base and the node in the absence of the electrical discharge, and for allowing the electrical discharge to be shunted away from the at least one internal component to be protected to ground, via the node and the base, in the presence of the electrical discharge.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: December 14, 1999
    Assignee: Hewlett-Packard Company
    Inventor: Steven E. Horvath
  • Patent number: 6002564
    Abstract: An overcurrent protection thick-film resistor device and overcurrent protection circuit employing the same are provided. Overcurrent (e.g., surge current) flows into the overcurrent protection circuit due to electrical shorting between external cables and power lines in communication networks. The thick-film resistor suppresses sparks due to such overcurrent, which would otherwise negatively affect peripheral parts or components disposed around the overcurrent protection circuit. This function is achieved by providing a thick-film resistor having an elongated meander or spiral shape, and also having a width-reduced section at one location of the thick-film resistor. Any sparks will predictably occur at this width-reduced section. A casing or other spark-dampening mechanism can be disposed selectively around the width-reduced section of the thick-film resistor.
    Type: Grant
    Filed: December 2, 1997
    Date of Patent: December 14, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Masashi Ohtsuchi
  • Patent number: 5995350
    Abstract: A temperature sensitive circuit interrupting arrangement includes a temperature controlled relay that will open to disconnect a load, such as a common household appliance or utensil, from a power source when the amount of heat produced by any one of a plurality of electrically conductive items coupling power from the power source to the load causes a sensed temperature to rise above a pre-determined safety limit temperature. The rise in the sensed temperature may be due to a poor (resistive) contact, an over-current condition due to a malfunction of the load, or other common causes. The circuit interrupting arrangement may be incorporated in many forms of electrical devices including male plugs, female sockets, switches, dimmers, multi-outlet power strips, power cords, and ground fault interrupters.
    Type: Grant
    Filed: June 24, 1998
    Date of Patent: November 30, 1999
    Inventor: Robert Z. Kopelman
  • Patent number: 5986863
    Abstract: Electrostatic discharge (ESD) protection circuits include first and second pads on an integrated circuit and first and second well regions in the integrated circuit substrate. The first and second well regions include respective first and second circumferences or walls. First and second diodes are included in the respective first and second well regions. The first and second diodes are serially connected between the first and second pads. A first guard ring is included adjacent the first circumference, and preferably in the first well. The first diode is included within the first guard ring. A second guard ring is also preferably included adjacent the second circumference, and most preferably in the second well. The second diode is included within the second guard ring.
    Type: Grant
    Filed: January 5, 1998
    Date of Patent: November 16, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sae-Choon Oh
  • Patent number: 5973897
    Abstract: An electrostatic discharge (ESD) protection circuit with reduced high frequency signal distortion includes an additional input shunting diode and a voltage follower amplifier. This second diode and the original input shunting diode are connected in series between the circuit node to be protected and circuit ground so as to limit the voltage level at such node during an ESD event. The voltage follower amplifier maintains a substantially constant voltage across this second diode, thereby maintaining a substantially constant diode junction capacitance. Hence, with the introduction of this additional, serially connected junction capacitance of the second diode, the nonlinear input capacitance responsible for input signal distortion is reduced, plus with a substantially constant diode junction capacitance due to the use of the voltage follower amplifier, such reduced capacitance remains substantially more constant over variations in the input signal voltage.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: October 26, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Ion E. Opris, Joseph Biran
  • Patent number: 5969932
    Abstract: A power surge protection assembly for use in electrical panel boxes having multiple electrical components. The power surge protection assembly includes a bus bar connected to a power supply, typically ground. The power surge protection assembly additionally includes a suppression box having a top surface, a bottom surface, sides, and ends for encasing a power surge suppression circuit. A conductor extends outward from an end of the suppression box. A coupler is attached to the bus bar for receiving the conductor and mechanically coupling the suppression box to the bus bar and electrically coupling the suppression box to the power supply. A variety of conductors and couplers are disclosed including post, bar, and plug conductors and snap ring, clip, jack, and bore couplers. The power surge protection assembly is particularly adapted for stacking two or more surge suppression boxes.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: October 19, 1999
    Assignee: A.C. Data Systems, Inc.
    Inventors: Barry D. Ryan, Norm Janshen, Brad Herr, Mark Scuitti, Jim Wilson, Alexander C. Johnson, Jr.
  • Patent number: 5963407
    Abstract: A fast operating, electronic overvoltage protection device intended for a power transistor having at least one control terminal of the MOS type is disclosed. The device comprises a Zener diode associated with the power transistor and integrated together therewith in a semiconductor substrate, and a second transistor connected to the power transistor into a Darlington configuration and also connected to the Zener diode. The protection from overvoltages provided by the device is very fast in operation, and can be implemented in integrated form at reduced cost and without introducing parasitic elements.
    Type: Grant
    Filed: February 9, 1998
    Date of Patent: October 5, 1999
    Assignee: SGS-Thomson Microelectronics S.r.L.
    Inventors: Leonardo Fragapane, Romeo Letor
  • Patent number: 5959823
    Abstract: A tank-type surge arrester includes a zinc oxide element unit having zinc oxide elements, a top shield ring for earth insulation control disposed on top of the zinc oxide element unit, an upper shield ring disposed below the top shield ring in an upper section of the zinc oxide element unit, an expanded lower shield ring disposed below the upper shield ring in the upper section of the zinc oxide element unit, and tubular conductors disposed between the upper and the lower shield rings so as to be included in a vertical plane on an extension of a high-tension conductor.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: September 28, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Shingo Shirakawa, Satoshi Watahiki
  • Patent number: 5956220
    Abstract: An adaptive distance relaying system provides improved performance for parallel circuit distance protection. The system utilizes the parallel circuit's current, when available, in conjunction with measurements of voltage and current on the protected line to compensate for the zero sequence current mutual coupling effect. The sequence current ratio (zero or negative sequence) is used to avoid incorrect compensation for relays on the healthy circuit. If the parallel circuit current is not available and the line operating status is, the best zero sequence current compensation factors are selected accordingly as a next level adaptation. If both the parallel circuit current and line operating status are unavailable, a fallback scheme that offers better results than classical distance protection schemes is employed.
    Type: Grant
    Filed: February 5, 1998
    Date of Patent: September 21, 1999
    Assignees: ABB Power T&D Company Inc., ABB Network Partner AB
    Inventors: Damir Novosel, Yi Hu, Murari M. Saha
  • Patent number: 5956218
    Abstract: An earth-leakage circuit breaker has a totalizing current transformer, a magnetic trip device and switchgear with main current contacts for the main leads. A current-signal generator, a current sensor, a time-signal generator and an electronic timer wherein the switching value and response time of the circuit breaker are measured at predetermined intervals, compared with reference switching values and response times and, if these reference values are exceeded, an alarm is promptly given. During the measurement, a locking device prevents the main current contacts from opening and/or when predetermined limiting switching and response times are exceeded, the locking device opens the main current contacts and subsequently acts as a lock preventing the contacts from closing again, which is equivalent to fail-safe behavior. In addition, the switching value of the circuit breaker is multiplied by its response time and the product, which may exceed a particular constant value, is used for monitoring purposes.
    Type: Grant
    Filed: May 6, 1997
    Date of Patent: September 21, 1999
    Assignee: AEG Niederspannungstechnik GmbH & Co. KG
    Inventor: Rainer Berthold
  • Patent number: 5949634
    Abstract: An electrostatic discharge protection circuit comprises an NMOS transistor and a silicon-controlled rectifier. The NMOS transistor is configured with one source/drain region connected to a first node, and its gate as well as another source/drain region connected to a second node. The silicon-controlled rectifier comprises a PNP transistor, an NPN transistor, and a resistor. The PNP transistor is provided with a first emitter connected to the first node, a first base disconnected from the first node, and a first collector. The NPN transistor is provided with a second emitter connected to the second node, a second base connected to the first collector and a second collector connected to the first base. However, the resistor is connected between the second base and the second node. The NMOS transistor enters breakdown to trigger the silicon-controlled rectifier to conduct a discharge current when electrostatic discharge stress occurs between the first node and the second node.
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: September 7, 1999
    Assignee: Winbond Electronics Corporation
    Inventor: Ta-Lee Yu
  • Patent number: 5946171
    Abstract: An electrical transformer which is filled with a combustible coolant may experience a break in the electrical insulation within the transformer. This break in the electrical insulation may lead to an explosion or fire. A pressure sensor and a vapor sensor are preferably coupled to the enclosure to monitor the pressure and vapor content of the enclosure. An increase in pressure of the enclosure may indicate that an insulation breakdown has occurred. When an increase in pressure is detected, the coolant is partially drained from the enclosure. After draining some of the coolant, an inert gas may be injected into the bottom of the enclosure to stir the remaining coolant.
    Type: Grant
    Filed: May 19, 1997
    Date of Patent: August 31, 1999