Abstract: An electrical overstress (EOS) protection circuit for protecting an active circuit of an integrated circuit including first and second clamping circuits series connected between a first input and a first input/output of the EOS protection circuit and third and fourth clamping circuits connected between a first output of the protection circuit and a second input/output. In embodiments of the present invention an EOS protection circuit provides protection for an active circuit while enabling a voltage at an input pad to the active circuit to exceed a power supply reference by more than several volts and to be less than a ground reference by more than several volts.

Abstract: An overvoltage protection circuit is formed by a voltage clipping component disposed between two inputs of a circuit to be protected, and a current limitation device connected, in series with the voltage clipping component, between one of the inputs and a bias connection terminal.

Abstract: A hybrid surge protector architecture is configured to accommodate a plurality of replaceable L-shaped communication signal surge protection modules and a multi receptacle AC voltage terminal strip in the same housing architecture. The modules may be configured to provide surge protection for different types of communications signal lines. The hybrid surge protector has a housing structure which contains a floor, a vertical wall and convex cover. A first portion of the wall has an opening in which an AC voltage terminal strip is installed. A second portion of the wall has an aperture for a plurality of communication signal surge protection circuit modules. Hot and neutral leads of the terminal strip are coupled to input ports of the AC voltage surge protection circuit. A reference ground conductor for the terminal strip and the AC voltage surge protection circuit is mounted along the housing floor adjacent to the terminal strip.

Abstract: A circuit that protects electronic components from damage caused by current and voltage surges generated on signal or data transmission lines when an electrically energized host device is connected to or disconnected from a peripheral device. The circuit uses transistor elements to switch off or interrupt the signal or data transmission line thus protecting circuit elements from damage. The protective circuit is enabled automatically whenever the connection of ground pins between the peripheral and the host fails to be established, as opposed to enabling the protective circuit when a voltage surge or a current surge is detected by a circuit element. When the ground pins between peripheral and host are finally connected, the circuit automatically responds by allowing data and signals to be transmitted between the host and the peripheral.

Abstract: An input protection circuit protects semiconductor circuits from ESD voltages and excessive voltages. The protection circuit includes an input/output node, a resistor (or other resistive element), and a varistor. The resistor has a first end coupled to the input/output node and a second end coupled to a port of the protected circuit. The varistor has a first end coupled to a ground node and a second end coupled to the second end of the resistor. The electronic circuit is coupled to the second end of the resistor and the second end of the varistor.

Abstract: A high-tension transformer incorporates a protection module (35) housed in a space defined between the body (11) of the high-tension transformer (10) and its cover (14), with plug-in connectors (36, 36') to be fitted between the body (11) and the module. In particular, the invention is suitable for transformers employed in discharge-type tubular lighting fixtures used for neon signs.

Abstract: An electric device is provided as an interface between a permanent power source (e.g., an electric wall outlet) and an electrical appliance. The device operates to interrupt electrical power to the electrical appliance in response to an increase in temperature of either the power cord plug of the electrical appliance or the terminals of the permanent power source to a predetermined temperature. The electric device detachably couples to the electric power terminals of both the permanent power source and the electrical appliance and is sensitive to the temperature at the terminals. The device includes a thermostat which rests on a thermal barrier member in thermal communication with the terminals, and is responsive to heat generated at the terminals to interrupt electrical power from the permanent power source to the appliance.

Abstract: A multiple receptacle power outlet device where one or more of the receptacles is connected to individual timers which can be set independently to independently control the on/off cycles of its associated receptacle without regard to the other timers. One or more continuous on receptacles can also be included and the entire device powered through a surge suppressor, noise filter and a single pole, single throw master switch. The timers can be mechanical or electronic and LED's provided at each receptacle to indicate when AC current is supplied to an electrical device plugged into the associated receptacle.

Abstract: A CDM simulator for use with an integrated circuit having a terminal and for use with a grounding conductor, includes a cylindrical conductor, and a mercury lead switch contained in the cylindrical conductor, the mercury lead switch having a first end connected to the cylindrical conductor and a second end for connection to the terminal of the integrated circuit, and the mercury lead switch having a first length, the cylindrical conductor having an end closer to the terminal of the integrated circuit for connection to the grounding conductor in order to release electric charge from the integrated circuit to the grounding conductor, and the cylindrical conductor having a second length longer than the first length of the mercury lead switch.

Abstract: A building entrance protector which incorporates the functions of a splice tray and a protector module comprising factory wired fusible link circuits which are insulated from all other wiring. Quick connect terminal strips and a protector receptacle block speed installation and maintenance.

Abstract: Protective equipment in a bipole converter station of an installation for power transmission by means of a high voltage direct current having main circuits on the dc side of the station. The main circuits have two separate pole parts, one part for each one of the two poles of the station, and a bipole part that is common to both poles. Measuring means in the station form measurement signals which correspond to operating quantities of the station. The measurement signals are supplied to the protective equipment. The protective equipment, dependent on the measurement signals and in their quarters with predetermined algorithm, takes measures to avoid permanent faults by influencing the operation of the station. The protective equipment has a pole protective means for each pole part and a bipole protective means for protection of the bipole part.

Abstract: Systems and methods for reducing the thermal stresses between an integrated circuit package and a printed circuit board, each having different thermal coefficients of expansion, to minimize thermal fatigue induced by power management cycling. The thermal impedance of the convection cooling system used with the integrated circuit package is switched with the state of the power management signal. A fan on the integrated circuit package heat sink is energized when the integrated circuit is operated in a high power mode and disabled when the integrated circuit is in a low power mode initiated by the power management system. The switching is directly responsive to the power management system and without regard to integrated circuit package temperature. The switching of the fan alters the thermal impedance to reduce the extremes of the temperature excursion and to materially reduce the rate of change of temperature experienced by the integrated circuit package.

Abstract: An electrostatic discharge (ESD) protection structure for protection of a circuit to which an operation voltage is to be applied, comprising a silicon controlled rectifier (SCR) connected between ground and a pad of the circuit to be protected, the SCR including a resistor apparatus connected to the pad for controlling the breakdown voltage of the SCR, and apparatus for controlling the resistor apparatus to a high resistance value in the absence of the application of the operation voltage whereby the SCR is controlled to break down at a low ESD voltage which is lower than a circuit damaging voltage, and to be of low resistance value upon the application of the operation voltage whereby the SCR is controlled to break down at an ESD voltage which is higher than the low ESD voltage.

Abstract: An enhanced electrostatic discharge suppression circuit is disclosed for protecting integrated circuit chips from electrostatic discharges or other potentially damaging voltage transients on an input/output pad. The suppression circuit includes a discharge circuit, electrically coupled to the input/output pad, having a diode comprising a diffusion in a substrate well formed in a substrate. The diffusion is connected to the input/output pad of the integrated circuit. A capacitor is locally provided to couple the substrate well to the substrate. The capacitor is sized to maintain the diode in a forward-bias mode during the electrostatic discharge event, thereby facilitating dissipating of the electrostatic discharge. The capacitor comprises a trench capacitor, which depending upon the configuration, may function as a guard ring for the discharge circuit. Certain beneficial parasitic effects are also discussed in association with integration of a trench capacitor into the suppression circuit.

Abstract: An output circuit for an integrated circuit which provides protection for the integrated circuit during a charged device model (CDM) electrostatic discharge (ESD) event. The output circuit includes a first FET connected across a first voltage supply rail (V.sub.CC or ground) and an output pad. A first driving circuit drives the gate of the first transistor. One or more CDM ESD protection circuits are connected between the gate of the first transistor and the output pad. These protection circuits provide relatively low impedance current paths which minimize current flow through the gate oxide layer of the first FET during a CDM ESD event.

Abstract: A solid-state circuit breaker and current limiter for a load served by an alternating current source having a source impedance, the solid-state circuit breaker and current limiter comprising a thyristor bridge interposed between the alternating current source and the load, the thyristor bridge having four thyristor legs and four nodes, with a first node connected to the alternating current source, and a second node connected to the load. A coil is connected from a third node to a fourth node, the coil having an impedance of a value calculated to limit the current flowing therethrough to a predetermined value.

Abstract: A glass-to-metal hermetic seal device which is particularly adapted for application in high pressure and other hostile environments for suppressing or dissipating electrostatic energy incorporating an improved glass-to-metal hermetic seal. The interior of the device incorporates and creates an in-situ gas-filled electrical discharge tube. The gas is an ionizable gas and may conveniently comprise a mixture of nitrogen and Argon, although other ionizable gases such as Xenon may be used. The devices of the present invention utilize one or more electrodes which enter the gas-filled chamber, and when the electrical field of sufficiently high potential is created within the gas-filled chamber, the gas ionizes and becomes conductive so as to effectively dissipate the field.

Abstract: A load control module (1) for controlling switch gear (2) which, in use, connects a power source (3) to remotely located electrical load (4). The module (1) includes a sensor unit (9) associated with the load (4) for providing a signal indicative of predetermined operating parameters of the load and a controller (10) for receiving the signal and for selectively providing another signal to the switch gear (2) which isolates the load (4) from the power source (3) when the load (4) does not comply with required operating parameters.

Abstract: An improved power filter circuit is disclosed. The improvement concern providing a clamping device between a ground lead and a terminal of a safety circuit such that when the power filter has its hot and neutral leads properly connected to hot and neutral leads of a utility circuit, a switch of the safety circuit connects the clamping device to be between ground and neutral leads of the power filter circuit, but when the hot and neutral leads of a utility circuit are reversed, the switch of the safety circuit connects the safety circuit directly between the neutral and hot leads of the power filter circuit, thereby creating an indicator, such as a red light, that the hot and neutral leads are reversed, yet the clamping device is now not connected between the neutral and ground leads of the power filter circuit. Accordingly, the clamping device connected between the ground and neutral leads may be rated during normal operations at a lower value, e.g.

Abstract: A method and an apparatus for protecting an integrated circuit from electrostatic discharge. In one embodiment, a voltage reduction circuit coupled to a termination circuit are coupled between a power supply and ground. The disclosed voltage reduction circuit utilizes a cantilevered diode string coupled to a clad network. Coupled to the voltage reduction circuit and the termination circuit is a voltage divider circuit which is coupled between the power supply and ground. The voltage supplied to the voltage reduction circuit and the termination circuit is a lower voltage than the steady state power supply voltage and is a tolerable voltage for gate oxides of a low voltage process. In another embodiment of the present invention, a voltage reduction circuit utilizing a stacked gate scheme is coupled between the power supply and ground. A voltage divider circuit is used in this embodiment to provide a bias voltage. The bias voltage is supplied to the voltage reduction circuit and a control circuit.