Patents Examined by Steve Loke
  • Patent number: 8329539
    Abstract: In a semiconductor device having a recessed gate electrode and a method of fabricating the same, a channel trench is formed in a semiconductor substrate by etching the semiconductor substrate. A first semiconductor layer is formed on the semiconductor substrate that fills the channel trench. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer having a lower impurity concentration than the first semiconductor layer.
    Type: Grant
    Filed: May 8, 2006
    Date of Patent: December 11, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Won Ha, Kong-Soo Lee, Sung-Sam Lee, Sang-Hyun Lee, Min-Young Shim
  • Patent number: 7012019
    Abstract: A circuit barrier structure of a semiconductor packaging substrate and a method for fabricating the same, forming a metal conductive layer on an insulating layer of the substrate and a patterned resist layer on the metal conductive layer. The patterned resist layer has a plurality of holes to expose predetermined parts of the metal conductive layer. A metal barrier layer is formed on the resist layer and in the holes. A patterned circuit layer is electroplated in the holes of the resist layer after removing the metal barrier layer on the resist layer. The resist layer and the metal conductive layer underneath the resist layer are removed. Another metal barrier layer can be formed on the circuit layer. The patterned circuit layer is covered by the metal barrier layers to prevent damage from etching to the circuit layer and inhibit migration of metal particles in the circuit layer.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: March 14, 2006
    Assignee: Phoenix Precision Technology Corporation
    Inventors: Shih-Ping Hsu, Kun-Chen Tsai
  • Patent number: 6724021
    Abstract: A semiconductor device, such as a power MOSFET, Schottky rectifier or p-n rectifier, has a voltage-sustaining zone (20) between a first (21, 23, 31a) and second (22) device regions adjacent to respective first and second opposite surfaces (11, 12) of a semiconductor body 10. Trenched field-shaping regions (40) including a resistive path (42) extend through the voltage-sustaining zone (20) to the underlying second region (22), so as to enhance the breakdown voltage of the device. The voltage-sustaining zone (20) and the trenched field-shaping regions (40) are present in both the active device area (A) and in the peripheral area (P) of the device. A further resistive path (53) extends across the first surface (11), outwardly over the peripheral area (P). This further resistive path (53) provides a potential divider that is connected to the respective resistive paths (42) of successive underlying trenched field-shaping regions (40) in the peripheral area (P).
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: April 20, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Rob Van Dalen, Christelle Rochefort, Godefridus A. M. Hurkx