Abstract: A low level input pulse signal from T.sup.2 L logic is delivered to the it of a ground deck driver which is transformer-coupled to a floating deck driver. The leading edge of the input pulse serves to enable or trigger a first FET driver, which is coupled to the gates of a plurality of series-connected FETs via a first transmission line transformer. The triggering of the FET driver serves to turn-on the series-connected FETs so that the same delivers a high voltage signal to an output load. A second FET driver is coupled to the gates of another plurality of series-connected FETs, which serve as a "tail-biter" to terminate the power to the output load. And, a third FET driver is coupled to the gates of the first-mentioned series-connected FETs to turn the same to the OFF state. The second and third FET drivers are coupled to their respective series-connected FETs via respective transmission line transformers.