Abstract: In a first aspect, a first method is provided that includes the steps of (1) transmitting a first signal representative of a test operation from a test circuit to a memory via a first signal path; (2) transmitting a second signal, synchronized with the first signal, from the test circuit to the memory via a second signal path; and (3) initiating the test operation on the memory in response to the second signal arriving at the memory. Numerous other aspects are provided.

Abstract: Various embodiments of the present invention relate to a device for testing an integrated circuit. According to one embodiment, the device comprises a first connector coupled to receive a device under test and a second connector coupled to receive compressed test data by way of test equipment. The device also comprises a decompressor coupled to receive compressed test data, and provided decompressed test data to the device under test. Embodiments implementing two different clocks to improve the speed of testing integrated circuits are also disclosed. Various methods for coupling test signals to a device under test are also disclosed.

Abstract: A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.

Abstract: An apparatus for testing integrated circuits is disclosed. The apparatus for testing integrated circuits comprises an integrated circuit and a tester. The integrated circuit undergoing testing receives an input signal, and outputs an output signal from a first output terminal or a second output terminal according to a first pulse width of the input signal, and outputs an error signal according to a difference between the first pulse width and a second pulse width. The tester outputs the input signal according to the output signal and the error signal.

Abstract: Methods and apparatus sort integrated circuits by maximum operating speed (fmax). The timing for a first set of critical timing paths is statistically characterized. The first set can be, for example, the set of all critical timing paths. For example, the timing can be generated by using static timing analysis (STA). The timing for a second set of critical timing paths is statistically characterized. The second set can be, for example, a sample set of critical timing paths that are measurable or are measured for a device during test. The timing can be based on STA, derived from a known good device, and the like. A device under test (DUT) is tested, and the timing for the second set of critical timing paths is determined. A fitting technique is used to fit the expected device characteristics and the measured data for the DUT, and in one embodiment, the parameters used for fitting are applied to the first set of critical timing paths, which are then used to determine an appropriate fmax for the DUT.

Abstract: A technique is provided for detecting errors in persistent memory, such as flash memory, where values of data items are stored at memory locations added consecutively to one end of the already-allocated memory segment. When a new location is added, a pointer to the address of the new location is stored at the location of a preceding value for that item. The address of the latest location is determined (21) whenever power is reapplied. The pointer fields of the locations are searched (24) for any pointer whose value is greater than the address of the last location. If such a pointer value is found, this indicates that an error occurred when writing the pointer value, for example because power was removed before completion of the pointer writing cycle. The error can be corrected by changing the pointer value to the address of the last location (27).

Abstract: An information input unit inputs functional configuration information representing a function of a device to be validated. A condition input unit inputs conditions concerning input/output sequence that is given to the device. A function generation unit generates a validation item function that fulfills all of the conditions based on the functional configuration information. An extraction unit extracts a combination of configuration elements that constitute the functional configuration information as a validation item based on the validation item function.

Abstract: JTAG test equipment arranged to establish an asynchronous data transmission connection with a JTAG-compatible device under test for the transmission of test data between test access ports (TAP) in the test equipment and device under test. The test data is synchronized at reception before the test access ports (TAP). The test equipment includes a computer program for adapting a test data sequence arriving in the format defined by the test access port for transmission on an asynchronous transmission path, and a transceiver (TR1) for adapting the test data sequence and transmitting it through the asynchronous data transmission connection to the device under test.

Abstract: A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.

Abstract: A semiconductor device-testing apparatus which is capable of testing semiconductor devices simultaneously by a simple construction. A plurality of latch circuits latch output signals outputted from a plurality of DUTs having the same test signal “test” inputted thereto. A P-S conversion circuit sequentially outputs an expected value signal “exp”, which is an expected value of signals that the DUTs should output in response to the test signal “test”, and a plurality of latched signals, for a latch time period. An encoder circuit compares the latched signals with the expected value signal “exp”. A memory stores the latched signals and the expected value signal “exp” delivered from the P-S conversion circuit, when the latched signals do not agree with the expected value signal “exp”. A determination circuit determines the quality of each of the DUTs, based on the latched signals and the expected value signal “exp” stored in the memory.

Abstract: Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least one bits stored in the first register may correspond one of the at least one test MRS codes stored in the second register.

Abstract: A test device for a semiconductor memory device includes a clock frequency multiplier, a data input buffer, a test data generator and a data output buffer. The clock frequency multiplier multiplies an external clock signal having a relatively low frequency provided from an external test device to generate an internal clock signal having a relatively high frequency. The data input buffer buffers test pattern data provided in synchronization to the external clock signal to output the buffered test pattern data. The test data generator generates test data that is to be synchronized to the internal clock signal, using the outputted test pattern data based on a first or a second control signal. The data output buffer outputs the generated test data to a memory core of the semiconductor memory device. The test device generates various test data suitable for a memory test at a high operating speed.

Abstract: A system and methods to transfer data between a testing interface and an IC. The system may include a synchronization subsystem to monitor the transitions of the test interface clock and/or IC clock to determine a clock adjustment appropriate to substantially synchronize the clocks. In certain implementations, a synchronization unit on an IC under test counts a predetermined number of transitions of an internal clock of an embedded device and generates a signal upon reaching a terminal count, which signal is received by a host controller associated with a JTAG test fixture. In such implementations, the host controller determines the number of IC clock cycles that occurred during the predetermined number of IC clock cycles and synthesizes a synchronized JTAG clock that is a integral fraction of the IC clock.

Abstract: A plurality of defect management areas (14A, 14B, 14C) are arranged on a write once type recording medium (10). Spare areas (12, 13) are divided into a plurality of partial spare areas (12A to 13B) and the defect list (21) is divided into partial defect lists (21A to 21D) so as to correspond to this. When recording data is recorded in a partial spare area, only the partial defect list corresponding to the partial spare area is recorded in the defect management area. In one defect management area, all the defect lists constituting the latest defect list are recorded.

Abstract: Systems and methods for performing logic built-in self-tests (LBISTs) in digital circuits, where boundary scan chains in functional blocks of the circuits can be selectively coupled/decoupled to isolate the functional blocks during LBIST testing. In one embodiment, processor cores of a multiprocessor chip are isolated and LBIST testing is performed to determine whether any of the processor cores is malfunctioning. If none of the processor cores malfunctions, the processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor is fully functional. If one or more processor cores malfunctions, these processor cores are isolated and the remaining processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor operates properly with reduced functionality.

Abstract: An analog base-band (ABB) chipset of a mobile communication system comprises a memory configured to store a test pattern, a test control unit configured to generate a control signal during a test mode, an ABB unit configured to perform a test operation by receiving the test pattern from the memory in response to the test control signal and to output data of the test pattern to the memory in response to the test control signal, and a path selection circuit configured to form a flow path of the test pattern in the ABB unit in response to the test control signal.

Abstract: A test method is described in which a signal from a tester enters a memory chip or memory module into a special test mode. The special test mode allows leakage defects connected to bit lines to be detected using bit line sense amplifiers. A first test command is issued by a tester, after which a word line is activated. The tester issues a second test command, delayed from the first test command, during the special test mode to turn-on the memory bit line sense amplifiers. The delayed second test command allows sufficient time for the leakage from defects at the crossing of the bit lines and the word line to charge capacitance of the bit lines and allow detection by the sense amplifiers.

Abstract: An object of the invention is to provide a boundary scan controller that allows a boundary scan to be executed and also allows a semiconductor apparatus to be manufactured in such a manner that the same type of semiconductor circuit chips are stacked. When identification data stored in memory means (85) is compared with fixed data held in fixed-data holding means (87) by comparison means (88) and the identification data is coincident with the fixed data, a data derivation section (89) outputs the same data as data which is outputted from an output section (86). In a boundary scan test, a data derivation section (89) of a boundary controller (80) provided for each semiconductor circuit chip is connected to the same bus line. When the identification data is not coincident with the fixed data, the data derivation section (89) can be substantially disconnected from the bus line.

Abstract: A CAM device that performs operations on-chip during testing. The CAM device can, for example, include circuitry that compares search results with an expected address to determine whether the expected address is defective. The CAM can be tested by applying search data and the expected address to the CAM at the same time, and determining if a match occurs at the expected address. In another approach, a reset match enable is used to limit the search to only a CAM memory location that has been written to, thereby limiting the test search to only the location containing test data.

Abstract: Apparatus and method for testing a CDMA integrated circuit including a demodulator for correlating input data with one of a set of codes and a test data pattern generator for spreading input test data with one of the set of codes to form a spread test data and providing the spread test data to the demodulator. The set of codes may be combined with the input test data to generate a set of spread test data which are then fed to the various components of the CDMA chip for testing the various components. In one embodiment, each one of the set of codes comprises a scrambling code and a spreading code.