Patents Examined by Steven H. Y. Loke
  • Patent number: 5391898
    Abstract: An IGBT has an emitter bypass structure. The interval D between N emitter regions is adapted to be larger than two times of a channel length L in order to effectively decrease a channel width to effectively decrease a saturation current. A high concentration region may be provided in a P base region, which is closer to the end portion of the P base region than the emitter regions between the emitter regions, so that the channel width can be effectively decreased even without the relation of D>2L. A channel width per unit area W.sub.U may be in a range of 140 cm.sup.-1 .ltoreq.W.sub.U .ltoreq.280 cm.sup.-1 in an IGBT of a breakdown voltage class of 500-750 V or 70 cm.sup.-1 .ltoreq.W.sub.U .ltoreq.150 cm.sup.-1 in an IGBT of a breakdown voltage class of 1000-1500 V, so that an IGBT having a short-circuit withstandability and a latch-up withstandability suitable for an inverter can be implemented.
    Type: Grant
    Filed: August 10, 1992
    Date of Patent: February 21, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroyasu Hagino
  • Patent number: 4882612
    Abstract: In a power semiconductor device according to the present invention, a sheet, formed of a soft metal such as Ag, is provided on that portion of a pressing control electrode which is brought into contact with an Al gate electrode of a pellet. By means of this sheet, it is possible both to apply a strong pressing power to the Al gate electrode and to reduce the contact resistance between the two electrode. Since an excessive amount of heat is not produced on account of the contact resistance, the semiconductor device can be protected against being damaged.
    Type: Grant
    Filed: May 4, 1987
    Date of Patent: November 21, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasunori Usui, Hiroshi Okamura, Yoshinari Uetake, Takashi Fujiwara