Abstract: A rectifying contact including a refractory metal carbide layer on a polycrystalline diamond layer provides high temperature operation and may be included in semiconductor devices, such as diodes and field effect transistors. The refractory metal carbide layer forms a substantially chemically non-reactive interface with the polycrystalline diamond. A single layer of substantially stoichiometric proportions of the refractory metal layer is provided in one embodiment of the rectifying contact. Another embodiment includes a second metal-rich refractory metal carbide layer on the stoichiometric layer. Yet another embodiment includes a carbon-rich refractory metal layer between the stoichiometric layer and the polycrystalline diamond layer. A metal field effect transistor including the rectifying contact may also be fabricated.

Abstract: A semiconductor device with a small gate-source capacitance is fabricated by growing a semiconductor epitaxial layer of a first conductivity type on a substrate. Two metal layers that are etched at different rates are successively deposited on the epitaxial layer. The metal layers are dry-etched to form a gate electrode including a wider (larger gate length) upper gate electrode section and a narrower (smaller gate length) lower gate electrode section. The upper gate electrode section is used as a mask for implanting a dopant impurity into the semiconductor epitaxial layer to form a source region having an edge close to but not extending beneath the lower gate electrode section.

Abstract: A contact structure for connecting a semiconductor device to a wiring electrode includes a semiconductor layer forming a part of the semiconductor device. A first contact layer of reduced resistivity covers a surface of the semiconductor layer. An insulating structure is provided on the first contact layer so as to bury the first contact layer underneath. A penetrating hole is opened through the insulating structure so as to expose a part of the first contact layer. A second contact layer of reduced resistivity is provided on the part of the first contact layer exposed by the penetrating hole. The second contact layer extends from a bottom of the penetrating hole along its side wall. A conductor layer forms the wiring electrode provided on the second contact layer.

Abstract: A high current, high voltage transistor which can be easily electrically stacked to extend the voltage range and uses less silicon area than a conventional stacked transistor configuration and a configuration of field plates that provide the greatest breakdown voltages with the highest ohmic values. Also, a star shaped field plate design which provides the greatest breakdown voltages with the highest ohmic values. The field plate is constructed using several concentric rings connected by fingers that are wider at towards the center of the concentric rings and narrower towards the perimeter of the concentric rings.

Abstract: A Conductor Insulator Semiconductor (CIS) heterojunction transistor. The CIS transistor is on silicon (Si) substrate. A layer of n type Si is deposited on the substrate. A trench is formed through the n type Si layer, and may extend slightly into the substrate. The trench is filled with an insulator, preferably SiO.sub.2. A layer of p type Si.sub.1-z Ge.sub.z (where z is the mole fraction of Ge and 0.1.ltoreq.z.ltoreq.0.9) is deposited on the n type Si layer. A p.sup.+ base contact region is defined in the p type Si.sub.1-z Ge.sub.z region above the oxide filled trench. A n type dopant is ion implanted into both the Si.sub.1-z Ge.sub.z and n Si layers and may extend slightly into the substrate, forming a collector region. A thin oxide layer is deposited on the Si.sub.1-z Ge.sub.z layer and a low work function metal such as Al, Mg, Mn, or Ti is selectively deposited on the thin oxide and to define an emitter. Alternatively, the emitter may be p.sup.+ polysilicon.

Abstract: Semicondctor devices having a curved P-N junction in an active area of the device and an edge passivation region extending from the active area to an edge region of the device include an electrically resistive ribbon that spirals outwardly from the active area to the edge of the device so that a voltage difference between the active area and the edge region is spread along the length of the ribbon. The ribbon may take the form of a linear resistor or may include plural diodes. The distance between radially overlapping portions of the spiralling ribbon and the cross-sectional area of the ribbon may be varied to spread the equipotential lines in the device so as to reduce the effect of the curved P-N junctions on the breakdown voltage of the device.

Abstract: A semiconductor device without erroneous operation and deterioration of characteristics in a transistor even when an impurity region is formed in self-alignment by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. This semiconductor device includes a gate electrode formed of a polycrystal silicon layer 4b having the crystal orientation of the crystal grains arranged in a definite orientation. By implanting ions at a predetermined angle with respect to the crystallographic axis of the crystal grains of the polycrystal silicon layer 4b in forming a p.sup.+ impurity region 5 by ion implantation using the gate electrode as a mask, the channeling phenomenon where ions pass through the gate electrode is prevented. Therefore, generation of erroneous operation and deterioration of characteristics in a transistor are prevented in forming an impurity region in self-alignment by ion implantation using the gate electrode as a mask.

Abstract: A semiconductor device (12) with reduced high voltage termination area and high breakdown voltage. The device comprises first and second field shield plates (46), (48). The first field shield plate (46) is disposed above a high voltage first impurity region (22) and a junction extension doped region (42) and is in contact with a conductive material (26) which comprises the high voltage terminal of the device (12). A second field shield plate (48) is disposed above a low voltage second impurity region (30) and the junction extension doped region (42) and is covered by an extended portion (35) of a low voltage source contact (34).

Abstract: An MOS transistor has a source region, a drain region, first gate electrode with a first channel zone allocated to it, second gate electrodes having a second channel zone allocated to it, and a third gate electrode with a corresponding third channel zone. The second channel zone is more highly doped than the base material in which the MOS transistor is formed, while the third channel zone is more lightly doped than the second channel zone. The second and third gate electrodes are conductively connected so that higher drain voltages are accommodated at high-frequencies while avoiding tunnel punch-through.

Abstract: The semiconductor device is composed of a thyristor and a MOSFET cascade-connected. The thyristor includes a bipolar transistor cascade-connected with the MOSFET, the base (p.sup.-- semiconductor region) of which is adapted to be punched through by the application of a working voltage. Thus, the thyristor can easily be latched and unlatched in response to the turn-on and turn-off of the MOSFET. Thus the semiconductor device can be securely on/off controlled by only the single gate (G) of the MOSFET. By using such semiconductor device as a switching element in a flash control device, a high performance flash control device with high flashing efficiency is provided.

Abstract: A diamond film FET according to the present invention comprises a semiconducting diamond layer, a gate, a source, and a drain, wherein said semiconducting diamond layer comprises a semiconducting highly-oriented diamond film grown by chemical vapor deposition, and at least 80% of the surface area of said diamond film consists of either (100) or (111) crystal planes, and the differences {.DELTA..alpha., .DELTA..beta., .DELTA..gamma.} of Euler angles {.alpha., .beta., .gamma.}, which represent the orientations of either (100) or (111) crystal planes, simultaneously satisfy the following relations between the adjacent crystal planes: .vertline..DELTA..alpha..vertline..ltoreq.5.degree., .vertline..DELTA..beta..vertline..ltoreq.5.degree. and .vertline..DELTA..gamma..vertline..ltoreq.5.degree..

Abstract: An electrostatic discharge (ESD) protection device for protecting a high voltage operating circuit having a high voltage input terminal is disclosed. The ESD protection circuit has a substrate, a first diffusion region formed in the substrate connected to the high voltage input terminal, a second diffusion region formed in the substrate connected to ground, a field oxide layer over the substrate having a thickened region extending into the substrate between the first and second diffusion regions, and a drift region formed in the substrate and located between the first diffusion region and the thickened field oxide layer. These regions are so arranged to move the point of avalanche breakdown away from the first diffusion/field oxide interface, so that the avalanche breakdown voltage is lower than that of the protected circuit while simultaneously preventing avalanche included bipolar feedback in the protection device.

Abstract: A trench MOS Schottky barrier rectifier includes a semiconductor substrate having first and second faces, a cathode region of first conductivity type at the first face and a drift region of first conductivity type on the cathode region, extending to the second face. First and second trenches are formed in the drift region at the second face and define a mesa of first conductivity type therebetween. The mesa can be rectangular or circular in shape or of stripe geometry. Insulating regions are defined on the sidewalls of the trenches, adjacent the mesa, and an anode electrode is formed on the insulating regions, and on the top of the mesa at the second face. The anode electrode forms a Schottky rectifying contact with the mesa.

Abstract: A silicon on insulator integrated circuit device is provided which comprises a substrate (10), a buried oxide layer (12), and an outer silicon layer (14). A buried p-layer (16) and a buried n-well region (26) are formed in order to position p-n junctions beneath n-channel and p-channel devices respectively formed in the outer silicon layer (14) outwardly from the p-layer (16) and (n)-well (26).

Abstract: Insulated Gate Field Effect Transitor (IGFET) having a reduced channel length without deteriorating an electric field relief effect includes a channel stop, located below a channel region, having a peak impurity concentration. A depth of the peak impurity concentration from the substrate surface is deeper than a bottom surface of source and drain regions that provides an Lightly Doped Drain structure.

Abstract: A lead frame for a semiconductor device and a method for manufacturing the semiconductor device using the frame, the lead frame comprising a dice pad, inner leads, tie bar, outer leads and a thin metal layer of lead which is hard to melt and is easily transformed formed on the surface of that portion of the inner leads, outer leads and the tie bar which is not covered with the sealing resin. In injection molding of a resin material on the lead frame with a semiconductor chip therein, the gap between the lead frame and the mold is filled while the thin metal layer is transformed by the clamping pressure, so that the bur may be prevented from being generated.

Abstract: A novel plastic molded chip carrier package for an integrated circuit chip has a carrier member molded of a plastic material to which are integrally embedded a plurality of I/O pins and a conductor member for interconnection between the terminals of the chip and the corresponding I/O pins to provide a unitary construction obtained at a single molding process. This plastic molded chip carrier package is preferred to have integral positioning studs which project in the same direction of the I/O pins for abutment against a printed circuit board for mounting the package in a spaced relation thereto with the I/O pins plugged into metallized through holes provided in the board.

Abstract: A touch sensitive light emitting diode comprising a diode (10) encapsulated in a plastics dome (11) and externally operable touch sensitive switching means positioned within the dome, the switching means including an output (18) to external electronics and the diode providing visual indication of the state of the switching means. The switching means may be a resistive touch switch, a voltage detection touch switch, a capacitance detection touch switch, or a proximity detection touch switch. The switching means may also be in the form of a stress/strain sensitive element (130) or a light sensitive element (71) positioned within the dome (11) to detect an object or finger-tip in proximity to the dome. The light emitting diode may also include an integrated circuit (69) positioned within the dome (11).