Abstract: A device and method of predistortion linearization that account for both EVM and spectral mask are disclosed. The device and method are based on transforming the predistorter optimization problem from the time domain to the frequency domain, and weighting the equations according to one or more desired objectives. One objective focuses on abiding by the spectral mask, whereas another objective focuses on improving the EVM.

Abstract: Methods and apparatus for Class-D amplifier circuits with improved power efficiency. The circuit has an output stage with at least first and second switches and a modulator that receives an input signal to be amplified, SIN, and a first clock signal fSW. The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability whilst reducing switching power losses.

Abstract: A circuit includes an amplifier configured to amplify an input signal and generate an output signal. The circuit also includes a tuning network configured to tune frequency response of the amplifier. The tuning network includes at least one tunable capacitor, where the at least one tunable capacitor includes at least one micro-electro mechanical system (MEMS) capacitor. The amplifier could include a first die, the at least one MEMS capacitor could include a second die, and the first die and the second die could be integrated in a single package. The at least one MEMS capacitor could include a MEMS superstructure disposed over a control structure, where the control structure is configured to control the MEMS superstructure and tune the capacitance of the at least one MEMS capacitor.

Abstract: An amplifier receives a differential signal and, in response, generates a first negative input current and a first positive input current. In a first operating mode, the amplifier receives a second differential signal, and, in response, generates a second negative input current and a second positive input current. In a second operating mode, the amplifier receives the second differential signal, and, in response, generates a third negative input current and a third positive input current. When the device is operating in the first operating mode, the first negative input current is summed with the second negative input current and the first positive input current is summed with the second positive input current. When the device is operating in the second operating mode, the first negative input current is summed with the third negative input current and the first positive input current is summed with the third positive input current.

Abstract: A circuit includes an amplifier output stage that includes a high switch and a low switch that generates a pulse width modulated (PWM) output signal to provide a load current to a load in response to a PWM input signal. The circuit includes a high gate drive that drives the high switch with a PWM high drive signal derived from the PWM input signal. This includes a low gate drive that drives the low switch with a PWM low drive signal derived from the PWM input signal. The circuit includes an edge corrector that adjusts at least one of a leading edge and a trailing edge of the PWM input signal to compensate for response time differences with respect to a direction of the load current to the load.

Abstract: An apparatus includes a voltage divider circuit and a reference amplifier coupled to the voltage divider circuit. The reference amplifier is configured to provide a feedback voltage to input circuitry of an amplifier.

Abstract: A dual mode, dual core power amplifier (PA) device includes a plurality of PA chains that generate output power according to an envelope tracking mode and a non-envelope tracking mode. The different modes can be selected to generate output power based on a set of predetermined criteria, which can be related to an input signal received by the system and related to a target power. A first PA chain with one or more PA cores is configured to operate in the envelope tracking mode based on at least a portion of the predetermined criteria being identified in the input signal and to generate output power with an envelope voltage supply that changes with an envelope of the input signal. In addition, a second PA chain with one or more PA cores can operate in a constant voltage supply mode or the non-envelope tracking mode according to the predetermined criteria.

Abstract: A power amplifier includes a clamping circuit configured to provide a clamped voltage from a power supply; an amplifier pair having first inputs coupled to the clamping circuit, second inputs and an output for providing an amplified signal; and a biasing circuit coupled between the clamping circuit and the second inputs. The biasing circuit is configured to adjust input bias voltages of the amplifier pair such that the output of the amplifier pair varies proportionally to a change of the power supply.

Abstract: An apparatus includes voltage-to-current conversion circuitry comprising a first voltage-to-current converter and a second voltage-to-current converter. The apparatus also includes a capacitor coupled to the first voltage-to-current converter and to the second voltage-to-current converter.

Abstract: The present invention provides a power gain-boosting technique for an amplifier in order to compensate for the decrease of Gmag in a transistor at high frequencies. A power gain-boosting technique of the present invention comprises the steps of: finding the Maximum Unilateral Gain or Mason's Invariant U of a transistor; designing a linear, lossless, reciprocal network embedding the transistor so that the final equivalent S-, Y-, or Z-parameters satisfy the condition: S ? 21 S 12 = Y 2 ? ? 1 Y 1 ? ? 2 = Z 2 ? ? 1 Z 1 ? ? 2 = - [ ( 2 ? U - 1 ) + 2 ? U ? ( U - 1 ) ] ; embedding the transistor into the linear, lossless, reciprocal network; and constructing simultaneous conjugate matching.

Abstract: The present invention implements a series of analog gain and phase correction circuits in each leg of the N-way Doherty to significantly reduce amplitude modulation to amplitude modulation (AM-AM) and amplitude modulation to phase modulation (AM-PM), distortion. The correction blocks comprise gain and phase corrections and optionally an additional gain block. The phase corrections include at least a phase offset and may include an optional non-linear element such as a diode pre-distorter. The pre-distortion circuitry is intended to reduce the necessary complexity of the DPD and reduce the DPD cost and power consumption. The gain and phase corrections can be calculated from computational optimization to minimize the AM-AM and AM-PM distortion. The gain and phase corrections can also be calculated from the AM-AM and AM-PM data which can be output from common DPD systems and laboratory characterization equipment.

Abstract: Improvement in linearity is achieved at low costs in a power amplifier module employing an envelope tracking system. The power amplifier module includes a first power amplifier circuit that amplifies a radio frequency signal and that outputs a first amplified signal, a second power amplifier circuit that amplifies the first amplified signal on the basis of a source voltage varying depending on amplitude of the radio frequency signal and that outputs a second amplified signal, and a matching circuit that includes first and second capacitors connected in series between the first and second power amplifier circuit and an inductor connected between a node between the first and second capacitors and a ground and that decreases a gain of the first power amplifier circuit as the source voltage of the second power amplifier circuit increases.

Abstract: An auto-zero circuit of an operational amplifier is disclosed, and the auto-zero circuit has: a micro-control unit and a digital potentiometer; the micro-control unit is used to obtain a voltage value of an offset voltage of the output end when there is no input in the operational amplifier, and generates a control signal which causes the voltage value of the offset voltage to be smaller than a first threshold value according to the voltage value of the offset voltage; the digital potentiometer is used to adjust a resistance thereof according to the control signal.

Abstract: An apparatus is provided. The apparatus includes a calibration circuit configured to generate a reference signal and at least one differential circuit each being configured to operate at a calibrated transconductance over process or condition variations based on the reference signal. The calibration circuit may be configured to generate the reference signal independent of the at least one differential circuit. A method for operating at least one differential circuit is provided. The method includes generating a reference signal and operating the at least one differential circuit at a calibrated transconductance or gain over process or condition variations based on the reference signal. The reference signal may be generated independently of the at least one differential circuit.

Abstract: A differential amplification circuit includes: a first input node; a second input node; a first output node; a second output node; a first transistor having a gate coupled to the first input node and a source coupled to a first node; a second transistor having a gate coupled to the second input node; a third transistor having a drain coupled to a drain of the first transistor; a fourth transistor having a gate coupled to a gate of the third transistor; a first resistor; a second resistor; a fifth transistor having a gate coupled to the drain of the first transistor; a sixth transistor having a gate coupled to the drain of the second transistor; a seventh transistor having a source coupled to the first node; an eighth transistor having a gate coupled to a gate of the seventh transistor; a third resistor; and a fourth resistor.

Abstract: This disclosure relates generally to power amplification devices and methods of operating the same. The power amplification devices are capable of reducing (and possibly cancelling) modulation of a ripple variation of a supply voltage level of a supply voltage onto a radio frequency (RF) signal. In one embodiment, a power amplification device includes a power amplification circuit configured to amplify an RF signal with a supply voltage such that a ripple variation in a supply voltage level of the supply voltage is modulated onto the RF signal in accordance with a conversion gain. However, the power amplification device also includes a plurality of ripple rejection circuits. The plurality of ripple rejection circuits is configured to produce phase shifts and one or more amplitude shifts in the RF signal so as to reduce the conversion gain of the power amplification circuit.

Abstract: A wide-band single-ended-to-differential low-noise amplifier using a push-pull architecture with an input node coupled to the sources of a first PMOS transistor and a first NMOS transistor, a positive output node coupled to the drains of the first PMOS transistor and the first NMOS transistor, a negative output node coupled to the drains of a second PMOS transistor and a second NMOS transistor, and bias circuitry coupled to the gates of the first and second PMOS and first and second NMOS transistors. The source of the first PMOS transistor is coupled to the gate of the second PMOS transistor, the source of the first NMOS transistor is coupled to the gate of the second NMOS transistor, the source of the second PMOS transistor is coupled to a first supply voltage, and the source of the second NMOS transistor is coupled to a second supply voltage.

Abstract: A current sense circuit having a single opamp DC offset auto-zero capability that allows for continuous current sensing operation while at the same time providing for DC offset sensing and compensation. The single opamp design can operate in a first phase to sense and store a DC offset, while providing an output to drive an output stage of the current sense circuit. The single opamp design can operate in a second phase, using the sensed DC offset to generate an accurate output that can drive the output stage and which can be used in the first phase.

Abstract: An apparatus includes an operational amplifier and a plurality of capacitors coupled to an input terminal of the operational amplifier and configured to be selectively coupled to receive one of an input voltage signal and an output voltage signal of the operational amplifier.

Abstract: Provided is a low noise amplifier. The low noise amplifier includes an input transistor receiving and amplifying a signal, an output transistor amplifying the signal amplified by the input transistor, and an inverting unit inverting the signal which is amplified by the input transistor and applying the inverted signal to a gate of the output transistor.