Patents Examined by Steven Lake
  • Patent number: 7229885
    Abstract: A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed round the first gate layer and the second disposable layer. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion regions.
    Type: Grant
    Filed: January 6, 2004
    Date of Patent: June 12, 2007
    Assignee: International Business Machines Corporation
    Inventors: David V. Horak, Toshiharu Furukawa, Akihisa Sekiguchi
  • Patent number: 7061006
    Abstract: Structures and methods to inject electrons into an insulator from a semiconductor layer that are then collected in a thin layer of a direct semiconductor material which in turn emits light by bandgap recombination.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: June 13, 2006
    Inventor: Robert W. Bower
  • Patent number: 6912146
    Abstract: An NMOS field effect transistor may be utilized to drive the memory cell of a phase change memory. As a result, the leakage current may be reduced dramatically.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: June 28, 2005
    Assignee: Ovonyx, Inc.
    Inventors: Manzur Gill, Tyler Lowrey
  • Patent number: 6815794
    Abstract: Semiconductor devices with a multiple isolation structure and methods for fabricating the same are provided. In one aspect, a semiconductor device comprises a heavily doped buried layer having a first conductivity type, which is formed in a predetermined region of a semiconductor substrate, and an epitaxial layer having the first conductivity type, which covers an entire surface of the semiconductor substrate. A device isolation structure is disposed such that the device isolation structure penetrates the epitaxial layer and a portion of the semiconductor substrate to define a device region. The device isolation structure includes an upper isolation structure penetrating an epitaxial layer as well as a lower isolation structure formed in the semiconductor substrate under the upper isolation structure.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: November 9, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwa-Sook Shin, Kwang-Dong Yoo
  • Patent number: 6720651
    Abstract: A semiconductor plastic package excellent in heat diffusibility and free of moisture absorption, is structured by fixing a semiconductor chip on one surface of a printed circuit board, connecting a semiconductor circuit conductor to a signal propagation circuit conductor formed on a printed circuit board surface in the vicinity thereof by wire bonding, at least connecting the signal propagation circuit conductor on the printed circuit board surface to a signal propagation circuit conductor formed on the other surface of the printed circuit board or a connecting conductor pad of a solder ball with a through-hole conductor, and encapsulating the semiconductor chip with a resin. The printed circuit board has a metal sheet of nearly the same size as the printed circuit board and is nearly in the center in the thickness direction of the printed circuit board.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: April 13, 2004
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Morio Gaku, Nobuyuki Ikeguchi, Nobuyuki Yamane
  • Patent number: 6465845
    Abstract: A smart power device and method for fabricating the same is disclosed in which an impact ionization to a drain region is reduced thereby securing a wide SOA (Safe Operation Area) and improving current driving characteristics.
    Type: Grant
    Filed: February 10, 2000
    Date of Patent: October 15, 2002
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Jong Hak Baek
  • Patent number: 5243556
    Abstract: A sampling device operating as a buffer between a first data signal and a relatively slow processing device accepts the input signal and stores samples of it on a SAW traveling past an input electrode. A blocking potential is applied to a set of electrodes to store a set of charge packets with the SAW device. Packets are consecutively released at a slower rate accommodated to the needs of the next processing unit in line, to read out the sampled signal at a modified rate for intentional distortion of the input signal, for slowing the output stored signal rate, or for time reversal of the signal.
    Type: Grant
    Filed: February 22, 1991
    Date of Patent: September 7, 1993
    Assignee: United Technologies Corporation
    Inventor: Thomas W. Grudkowski
  • Patent number: 5124776
    Abstract: A semiconductor integrated circuit comprises a plurality of first hierarchical units of logic devices each including a plurality of bipolar logic devices having a polycell structure. The bipolar logic devices have a first standardized size in a first direction and are arranged in a second direction for a second standardized size in each first hierarchical unit. Each of the first hierarchical units is defined by first and second main edges extending in the second direction for the second standardized size, and first and second side edges extending in the first direction for the first standardized size. Each of the first hierarchical units consumes a generally identical electric power and has a first power feed system extending in the second direction for the second standardized size for feeding the electric power to the bipolar logic devices therein.
    Type: Grant
    Filed: March 13, 1990
    Date of Patent: June 23, 1992
    Assignee: Fujitsu Limited
    Inventors: Tetsu Tanizawa, Takehito Doi, Hideo Tokuda, Shigenori Ichinose
  • Patent number: 5091771
    Abstract: A very compact package for an electronic data module, which includes battery-backed memory. A two-part metal container is used, which has two shallow concave pieces which fit together. The integrated circuit (in a low-height package, such as a flat-pack or SOIC) is mounted on a very small flexible printed circuit board, which fits inside the container. Laterally spaced from the integrated circuit, on the other end of the small flexible board, the board end is sandwiched between a battery and a piece of elastic conductive material (such as conductive plastic foam). Thus, the battery is connected between one face of the container and a power conductor on the board. The piece of elastic conductive material makes contact between a data trace on the board and the other face of the container. Another trace on the board makes contact directly to the container face on which the battery's ground terminal is connected.
    Type: Grant
    Filed: May 15, 1989
    Date of Patent: February 25, 1992
    Assignee: Dallas Semiconductor Corporation
    Inventors: Michale L. Bolan, Robert D. Lee, James P. Manitt
  • Patent number: 5018002
    Abstract: A hermetic semiconductor chip package includes a conductive foil bonded to a contact pad of the chip and connected to an external lead of the package through an aperture in the insulating material of the package lid.
    Type: Grant
    Filed: July 3, 1989
    Date of Patent: May 21, 1991
    Assignee: General Electric Company
    Inventors: Constantine A. Neugebauer, Wolfgang Daum
  • Patent number: 4982251
    Abstract: A semiconductor element comprises its main part constituted of a polycrystalline silicon semiconductor layer containing 0.01 to 1 atomic % of fluorine atoms.
    Type: Grant
    Filed: April 17, 1990
    Date of Patent: January 1, 1991
    Assignee: Canon Kabushiki Kaisha
    Inventors: Katsumi Nakagawa, Toshiyuki Komatsu, Yutaka Hirai, Yoshiyuki Osada, Satoshi Omata, Takashi Nakagiri