Patents Examined by Steven Lohe
  • Patent number: 7026646
    Abstract: An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the control signal.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: April 11, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Timothy B. Cowles, Aron T. Lunde
  • Patent number: 6784469
    Abstract: A solid-state image pickup device includes: a plurality of light receiving portions arranged in a matrix, and a vertical transfer register which is four-phase driven by first, second, third and fourth transfer electrodes of a three-layer structure. The vertical transfer register is provided for each of columns of said light receiving portions. The first and third transfer electrodes of the first layer are alternately arranged in a charge transfer direction, and the adjacent two of the first and third transfer electrodes extend in parallel to each other between the light receiving portions. With this solid-state image pickup device, the accumulated charge capacity of each transfer region composed of the adjacent transfer electrodes for two-phases is equalized and the area of the light receiving portion is increased irrespective of variations in processed dimension between the transfer electrodes.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: August 31, 2004
    Assignee: Sony Corporation
    Inventors: Junji Yamane, Kunihiko Hikichi
  • Patent number: 6781153
    Abstract: A TFT (20) for controlling the power supplied to an element to be driven (50), such as an organic EL element which operates based on the supplied power, is provided between the element to be driven (50) and a power supply line VL. The TFT (20) and the element to be driven (50) are electrically connected to by a wiring layer (40). The contact position between the wiring layer (40) and the TFT (20) and the contact position between the wiring layer (40) and the element to be driven (50) are positioned so as to be distant from each other. Alternatively, at least the contact hole region of a first electrode (52) of the element (50) is covered by a flattening layer. With this structure, it is possible to realize a flatter surface on which to form, for example, the emissive layer of the element to be driven.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: August 24, 2004
    Assignee: Sanyo Electric Co., Inc.
    Inventor: Katsuya Anzai
  • Patent number: 6773948
    Abstract: A semiconductor light emitting device of the present invention includes: a substrate; a light emitting layer; a semiconductor layer of a hexagonal first III-group nitride crystal; and a cladding layer of a second III-group nitride crystal. A stripe groove is provided in the semiconductor layer along a <1, 1, −2, 0> direction.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: August 10, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinji Nakamura, Masahiro Ishida, Masaaki Yuri, Osamu Imafuji, Kenji Orita
  • Patent number: 6121685
    Abstract: Novel metal-alloy interconnections for integrated circuits. The metal-alloy interconnections of the present invention comprise a substantial portion of either copper or silver alloyed with a small amount of an additive having a low residual resistivity and solid solubility in either silver or copper such that the resultant electrical resistivity is less than 3 .mu..OMEGA.-cm.
    Type: Grant
    Filed: August 6, 1997
    Date of Patent: September 19, 2000
    Assignee: Intel Corporation
    Inventor: Donald S. Gardner