Patents Examined by Steven Rohe
  • Patent number: 6787927
    Abstract: A semiconductor device comprises a chip; a plurality of bonding pads provided on the chip; and a plurality of inner leads arranged opposite to the bonding pads. Further the semiconductor device comprises a plurality of bonding wires electrically connecting the bonding pads and the corresponding inner leads, respectively. Each of the bonding wires has a plurality of bends electrically isolated from conductive parts on the chip, and the bonding pads are arranged at optional positions on a surface of the chip. Hence the shorting of the chip by the bonding wires can be reliably prevented, the bonding wire having a high mechanical strength can be stably fed, the bonding pads may be optionally arranged on the chip, the degree of freedom of designing the layout of the internal circuit of the chip is high, and the semiconductor device and the wire bonding apparatus can be developed at a high efficiency.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: September 7, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Hiroshi Horibe