Patents Examined by Steven Snyder
  • Patent number: 9026580
    Abstract: Techniques for configuring validation rules in a client-server architecture, and for enforcing such validation rules are provided. A developer is enabled to configure a display screen for an application to enable a user at a client to input data. The developer is further enabled to input a validation rule that is configured to be applied to validate the data at the client and/or at a server. The validation rule is integrated into code of the application. During execution of the application, a client-side rules engine may be present to evaluate the validation rule at the client, and a server-side rules engine may be present to evaluate the validation rule at the server. The client-side rules engine and server-side rules engine may be configured to evaluate validation rules in an asynchronous manner.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: May 5, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Premanand Ramanathan, Daniel Seefeldt
  • Patent number: 9021162
    Abstract: A data processing apparatus may include a data conversion unit for, when converting a plurality of sequentially input data into conversion data of the same bit number as a data bus having a prescribed bit number and sequentially transferring the conversion data. The data conversion unit may include a first data generation unit, a second data generation unit for generating second data obtained by allocating a prescribed second number of input data in the input data not allocated to the first data, to the second bit range and a data coupling unit for coupling the first data and the second data to generate the conversion data having the bit number of the bus width of the data bus.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: April 28, 2015
    Assignee: Olympus Corporation
    Inventors: Ryusuke Tsuchida, Akira Ueno, Masami Shimamura, Yoshinobu Tanaka, Takashi Yanada, Tomoyuki Sengoku
  • Patent number: 9021163
    Abstract: A method, program and/or system for determining whether a data storage is encrypted. A file is written through a first path to the data storage. The file is read through a second path from the data storage. First data known to have been written in the file is compared to second data that has been read from the file. When the first data matches the second data, the first path is determined not to have encrypted the file when writing to the data storage. When the first data does not match the second data, the first path is determined to have encrypted the file when writing to the data storage.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 28, 2015
    Assignee: OPSWAT, Inc.
    Inventors: Benjamin Czarny, Jianpeng Mo, Boris Dynin
  • Patent number: 9009700
    Abstract: In one embodiment, a method includes: receiving, by a first computer system, a data stream transmitted from a second computer system over a network connection between the first computer system and the second computer system, wherein the data stream comprises executable code of a software program; extracting, by the first computer system, the executable code of the software program from the data stream; allocating, by the first computer system, an amount of dynamic memory for the executable code of the software program; loading, by the first computer system, the executable code of the software program directly into the allocated dynamic memory; and executing, by the first computer system, the software program by launching the executable code of the software program loaded in the allocated dynamic memory.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: April 14, 2015
    Inventor: Julian Michael Urbach
  • Patent number: 8997083
    Abstract: An administrator system can generate a version identifier for a computing system based on the software packages installed on a computing system. The version identifier can represent the software packages installed on the computing system. The administrator system can utilize the version identifier to manage a network of computing systems. The administrator system can compare the version identifiers of the computing system to verify that the computing system have the same software packages installed. Likewise, the administrator system can compare the version identifiers of the computing system to a test version identifier.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: March 31, 2015
    Assignee: Red Hat, Inc.
    Inventors: Seth Kelby Vidal, James Antill
  • Patent number: 8977787
    Abstract: A host computer accesses a storage volume via multiple paths and maintains path mode information identifying either an active or standby operating mode. An active-mode path is generally usable, and a standby-mode path is usable under exceptional conditions such as non-availability of an active-mode path. A reason identifier identifies a first operating condition causing the path to be placed in the standby mode. Upon a path-activating event for a standby-mode path, if there is a second operating condition indicating that the path should be maintained in the standby operating mode, then the path is maintained in the standby operating mode and the path mode information is set to identify the second operating condition, and otherwise the operating mode is set to active. A path-activating event can be a manual action by a user or automatic action such as expiration of an aging timer to re-attempt use of a standby path.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: March 10, 2015
    Assignee: EMC Corporation
    Inventors: Helen S. Raizen, Hitesh P. Trivedi, Robert J. Pellowski, Jimmy K. Seto
  • Patent number: 8966227
    Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Goro Sakamaki, Yuri Azuma
  • Patent number: 8966145
    Abstract: A data processing apparatus may include: a data conversion unit configured to designate one-transfer data as one transfer unit and designate a predetermined number of transfer units as one conversion unit when a plurality of input data sequentially input is converted into transfer data of which the number of bits is the same as that of a data bus having a predetermined number of bits, and the transfer data is sequentially transferred, and arrange the input data in the transfer data within the conversion unit. The data conversion unit may include: a data generation unit, a first data arrangement change unit, and a first data selection unit configured to sequentially select the changed data in which the position of the input data is changed by the first data arrangement change unit and output the selected changed data as the transfer data in the data conversion unit.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: February 24, 2015
    Assignee: Olympus Corporation
    Inventors: Ryusuke Tsuchida, Akira Ueno, Masami Shimamura, Yoshinobu Tanaka, Takashi Yanada, Tomoyuki Sengoku
  • Patent number: 8966628
    Abstract: Some embodiments provide a system that executes a native code module. During operation, the system obtains the native code module. Next, the system loads the native code module into a secure runtime environment. Finally, the system safely executes the native code module in the secure runtime environment by using a set of software fault isolation (SFI) mechanisms that constrain store instructions in the native code module. The SFI mechanisms also maintain control flow integrity for the native code module by dividing a code region associated with the native code module into equally sized code blocks and data blocks and starting each of the data blocks with an illegal instruction.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: February 24, 2015
    Assignee: Google Inc.
    Inventors: Robert Muth, Karl M. Schimpf, David C. Sehr, Cliff L. Biffle
  • Patent number: 8966437
    Abstract: A computer based method, system and apparatus specify graphical concrete syntax in a modeling language. The invention system declaratively describes the graphical concrete syntax of a diagram of a subject model. A mapping engine maps between (i) the graphical concrete syntax and (ii) the abstract syntax and corresponding diagram interchange syntax of the subject model. The declarative descriptions define structure of the graphical concrete syntax rather than a rendering (painting) logic of the graphical concrete syntax.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventor: Maged E. Elaasar
  • Patent number: 8959265
    Abstract: A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to write completion reports to the system memory, including first completion reports of a first data size and second completion reports of a second data size, which is smaller than the first data size.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: February 17, 2015
    Assignee: Mellanox Technologies Ltd.
    Inventors: Ofer Hayut, Noam Bloch, Michael Kagan, Ariel Shachar
  • Patent number: 8949489
    Abstract: Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Google Inc.
    Inventor: Arif Merchant
  • Patent number: 8949495
    Abstract: An input device with parallel multi-tasking capabilities is disclosed. The input device comprises a controller, a data assigning unit and a plurality of first communication end-points. The input device declares the plurality of first communication end-points as virtual peripheral devices with equivalent performance. When the input device is electrically connected to a host for data communication, the virtual peripheral devices with equivalent performance and a plurality of second communication end-points are respectively establish communication link of point-to-point correspondingly, so that the plurality of second communication end-points receive a plurality of operation slave data for reducing data communication time.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: February 3, 2015
    Assignee: Dexin Corporation
    Inventor: Shu-Sheng Chen
  • Patent number: 8943243
    Abstract: An apparent load is determined based on assigning weightings to commands based on various factors including, but not limited to, the limitations of the underlying storage media device(s), where the command queue fullness is viewed from that perspective rather than simply the number of commands outstanding in a storage media device. Also disclosed is the use of a positive bias and a negative bias to artificially influence the apparent load based on the read rate of storage media devices.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: January 27, 2015
    Assignee: Concurrent Ventures, LLC
    Inventors: Jesse D. Beeson, Jesse B. Yates
  • Patent number: 8943226
    Abstract: Disclosed is a storage device interface. The storage device interface includes a plurality of PCIe device request engines. These PCIe device request engines receive I/O commands formatted for a respective one of a plurality of PCIe storage device communication standards. The storage device interface also includes a plurality of PCIe device completion engines. These PCIe device completion engines receive notifications of command completions from a plurality of PCIe storage devices that communicate using the aforementioned plurality of PCIe storage device communication standards. These notifications are validated. If an error is detected, processing of notifications of command completions associated with that device are blocked until the error is resolved. The plurality of PCIe device request engines and the PCIe device completion engines operate concurrently to process received I/O commands and received command completions.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: January 27, 2015
    Assignee: LSI Corporation
    Inventors: Timothy E. Hoglund, Gary J. Piccirillo, James K. Yu
  • Patent number: 8943238
    Abstract: A system includes a serial interface, a peripheral device coupled to the serial interface, non-volatile memory, and a DMA controller including multiple linked channels. The various channels can be configured in different modes to facilitate the DMA controller performing various operations, such as data transfer, with respect to the non-volatile memory or the peripheral device.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: January 27, 2015
    Assignee: Atmel Corporation
    Inventors: Laurentiu Birsan, Jacques Tellier, Benoit Mouchel
  • Patent number: 8943103
    Abstract: A database management system implemented in a cloud computing environment. Operational nodes are assigned as controller-nodes, compute-nodes or storage-nodes. The number of operational nodes, and their assignment as compute-nodes or storage-nodes can vary. Queries specify tables, with each such table assigned to a respective group of storage nodes. The number of operational nodes executing a given query may change by (a) changing the compute-nodegroup associated with a connection, or (b) adding or removing nodes from the compute-nodegroup; and/or distributing data from the tables among the nodes in a storage nodegroup. State information is maintained for each client connection, such that steps are executed assuming that the state exists.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: January 27, 2015
    Assignee: Tesora, Inc.
    Inventor: Mrithyunjaya Annapragada
  • Patent number: 8930907
    Abstract: Described is a probabilistic concurrency testing mechanism for testing a concurrent software program that provides a probabilistic guarantee of finding any concurrent software bug at or below a bug depth (that corresponds to a complexity level for finding the bug). A scheduler/algorithm inserts priority lowering points into the code and runs the highest priority thread based upon initially randomly distributed priorities. When that thread reaches a priority lowering point, its priority is lowered to a value associated (e.g., by random distribution) with that priority lowering point, whereby a different thread now has the currently highest priority. That thread is run until its priority is similarly lowered, and so on, whereby all schedules needed to find a concurrency bug are run.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: January 6, 2015
    Assignee: Microsoft Corporation
    Inventors: Sebastian Carl Burckhardt, Pravesh Kumar Kothari, Madanlal S. Musuvathi, Santosh Ganapati Nagarakatte
  • Patent number: 8930590
    Abstract: An audio device and a method of operating the same are provided. The audio device includes a storage unit, a first memory and a second memory, a hardware decoder, a software decoder, a first direct memory access (DMA) block, a second DMA block, and a controller. The controller converts the audio device from an ultra low power mode in which the first PCM information is transmitted to an audio interface buffer through the first memory, the hardware decoder, and the first DMA block or a low power mode in which the second PCM information is transmitted to the audio interface buffer through the second memory, the software decoder, and the first DMA block to a normal mode in which the second PCM information is transmitted to the audio interface buffer through the second memory, the software decoder, and the second DMA block.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Kil-Yeon Lim
  • Patent number: 8924596
    Abstract: A shared counter resource, such as a register, is disclosed in the hardware, where the register representing how much free space there is in the command queue is accessible to one or more processing elements. When a processing element reads the “reservation” register, the hardware automatically decrements the available free space by a preconfigured amount (e.g., 1) and returns the value of the free space immediately prior to the read/reservation. If the read returns 0 (or a number less than the preconfigured amount), there was insufficient free space to satisfy the request. In the event there was insufficient space to satisfy the request the reservation register may be configured to reserve however much space was available or to not reserve any space at all. Any number of processing elements may read these registers and various scenarios are described where the input and output queues are accessible via various processing elements.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: December 30, 2014
    Assignee: Concurrent Ventures, LLC
    Inventors: Jesse D. Beeson, Jesse B. Yates