Abstract: A data processing system includes a commercial instruction processor (CIP) for executing decimal arithmetic instructions. The operands processed by the CIP include packed decimal and string decimal operands. The decimal arithmetic instruction includes descriptors for describing the characteristics of the operands. A register coupled to an arithmetic logic unit stores double words of the operands which are written into the register as double words, bytes or decimal digits. A multiplexer is responsive to control store signals and descriptor signals for generating write control signals which are applied to a read only memory. The read only memory output write signals select the decimal digit, byte or double word positions of the register for writing.

Abstract: In the aircraft navigation computer disclosed herein, a first voltage is generated which is varied as function of the position of a map strip and this voltage is compared with a second voltage which varies in accordance with the passage of time. A signal is generated when these voltages cross each other, signifying satisfaction of the navigation equation: distance=time.times.speed.

Abstract: A single-chip processor architecture is disclosed which permits the registers and control latches of the processor to be easily accessed without using instructions to achieve such access. The architecture provides for an internal access (IA) function which is enabled by applying an IA Request signal to an IA terminal of the processor. During the IA function, program execution in the processor is suspended and the registers and control latches may be accessed as if they were storage locations in a random access memory. After the IA function is enabled, the address of a register or control latch selected for access is applied to the Address/Data port of the processor, and an IA Control Code specifying the strobing of the Address/Data port is applied to the Status terminals of the processor. After strobing of the address, a second IA Control Code specifying either reading or writing of the selected register or control latch is applied to the Status terminals.

Abstract: A shared time-of-day (TOD) clock modification bit is used in a multiprocessing system in which the timing facilities in two or more CPUs are implemented as a function of a single TOD clock. This bit helps avoid timer errors that occur as the result of one central processing unit (CPU) changing the TOD clock value while another CPU is executing an instruction which determines a CPU timer value. Whenever the microcode in any one of the CPUs reads the TOD clock, it obtains the Shared TOD Clock Modification Bit in addition to the TOD value. This bit indicates if the TOD clock read operation just completed is the first such operation executed by that CPU since the TOD clock was updated by another CPU sharing the same TOD clock. If it is, certain instructions take action to correct timer errors introduced by the change in the TOD clock value.