Patents Examined by Sue A. Purvis
  • Patent number: 8994595
    Abstract: An antenna for receiving and transmitting a signal is provided. The antenna includes a connection portion receiving and transmitting the signal, a first radiation portion and a second radiation portion. The connection portion includes a first end, a second end and a third end, wherein the first end is configured at a first distance from a ground. The first radiation portion is connected to the second end, and includes at least one folding area forming thereon at least one folding segment, wherein the folding segment and the connection portion have therebetween a shortest distance being a second distance. The second radiation portion is connected to the third end.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: March 31, 2015
    Assignee: Arcadyan Technology Corp.
    Inventors: Chih-Yung Huang, Kuo-Chang Lo, Sy-Ben Wang
  • Patent number: 8988286
    Abstract: A multi-band built-in antenna of a portable terminal is provided. The antenna includes a first antenna radiator on a front surface of a substrate (e.g., a main board), and a second antenna radiator on an opposite surface of the substrate. The substrate has ground surfaces on both sides separated from a non-ground area on which the radiators are disposed. The first radiator may be in the form of a Planar Inverted F Antenna (PIFA), with a first end branched off into two parts, one part used for power feeding and the other part electrically coupled to the ground surface. The first radiator has a portion that extends from the first end to an opposite end. The second radiator is continuous from the opposite end of the first radiator through a via (hole) in the main board.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ho Ahn, Seung-Hwan Kim, Austin Kim, Dong-Hwan Kim, Jae-Ho Lee, Sung-Min Her
  • Patent number: 8982000
    Abstract: A watch type mobile terminal includes a first case which includes a window; a second case coupled to the first case and having an area for mounting a plurality of components; and a third case coupled to the second case such that the plurality of components are positioned between the second case and the third case. The mobile terminal further includes an antenna positioned at a side portion of a case including the first case, the second case, and the third case. The antenna includes a first conductor which is attached to the plurality of components, substantially covered by the second case, and connected to a signal feeding portion; and a second conductor which is positioned to be separated from the first conductor such that the second conductor is electrically coupled with the first conductor and connected to a ground feeding unit to be connected to a ground.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: March 17, 2015
    Assignee: LG Electronics Inc.
    Inventors: Changil Kim, Jaehyuk Kang, Kyunghack Yi, Jonghun Kwon
  • Patent number: 8981997
    Abstract: An antenna includes an antenna element in which a predetermined electrode is provided on a dielectric base member and a substrate in which a predetermined electrode is provided on a base. A feed-terminal connecting electrode to which a feed terminal provided on the lower surface of the antenna element, an external-terminal connecting electrode to which an external electrode is connected, and a ground-terminal connecting electrode to which a ground terminal provided on the lower surface of the antenna element are provided on the upper surface of an ungrounded area of the substrate. A chip inductor is connected between the external-terminal connecting electrode and the feed-terminal connecting electrode, and a chip inductor is connected between the external-terminal connecting electrode and the ground-terminal connecting electrode. The shortcut of a current route achieved by each of the chip inductors is provided.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: March 17, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kengo Onaka, Kunihiro Komaki, Takashi Ishihara, Takuya Murayama, Tsuyoshi Mukai
  • Patent number: 8952856
    Abstract: A transmission/reception element includes: a plurality of metal layers each disposed with space from another; and a switch for controlling electrical coupling between the metal layers. The switch includes a contact-point group including a plurality of contact-point pairs each disposed in parallel between each two of the metal layers, and a drive section mechanically driving the contact-point group for state change of each of the contact-point pairs between in-contact and no-contact.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: February 10, 2015
    Assignee: SonyCorporation
    Inventors: Akira Akiba, Koichi Ikeda
  • Patent number: 8952863
    Abstract: An apparatus comprising an actuating substrate and an antenna in contact with the actuating substrate, the actuating substrate configured to undergo strain during actuation, wherein the strain in the actuating substrate varies the dimensions of the in-contact antenna and causes a change in the operational characteristics of the antenna.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: February 10, 2015
    Assignee: Nokia Corporation
    Inventors: Samiul Haque, Richard White
  • Patent number: 8947314
    Abstract: A mobile communication device includes an antenna structure having a dielectric substrate and an antenna. The dielectric substrate includes a ground portion, a first non-ground portion, and a second non-ground portion. The ground portion further includes a main ground and a protruded ground electrically connected to the main ground and extending between the first non-ground portion and the second non-ground portion. The first non-ground portion and the second non-ground portion are separated by the protruded ground. One edge of the protruded ground aligns with one edge of the dielectric substrate. The antenna includes a feeding portion located in the first non-ground portion and a radiating portion extending over the protruded ground and having a first end located in the first non-ground portion and electrically connected to the main ground and a second end of the radiating portion is located in the second non-ground portion and electrically connected to the main ground.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: February 3, 2015
    Assignee: Acer Inc.
    Inventors: Kin-Lu Wong, Fang-Hsien Chu
  • Patent number: 8947315
    Abstract: An antenna that resonates at each of at least operating two frequency bands includes a first LC parallel circuit having a first impedance between a feeding element and a feeding circuit, and a second LC parallel circuit having a second impedance between a parasitic element and ground. The feeding element and the parasitic element are configured such that multiple resonant frequencies are positioned between the two operating frequency bands in a case where the impedances of the first and second LC parallel circuits are set to 0, and the LC parallel circuits having the first and second impedances cause the multiple resonance frequencies to shift to an operating frequency band on the lower frequency side and to the higher frequency side, of the two operating frequency bands.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: February 3, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kengo Onaka, Tsuyoshi Mukai, Munehisa Watanabe
  • Patent number: 8928543
    Abstract: A gyrotropic metamaterial structure that include a plurality of chiral metamaterials forming one or more pairs of dipole structures. A plurality of lumped circuits are positioned between the one or more pairs of dipole structures. The lumped circuits have a plurality of subwavelengths antennas that are combined to change the polarization states of an incident polarized wave by producing Faraday-like rotation allowing for nomeciprocal propagation of the incident polarized wave.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: January 6, 2015
    Assignee: Massachusetts Institute of Technology
    Inventors: Zheng Wang, Marin Soljacic, Zhiyu Wang, John D. Joannopoulos, Lixin Ran
  • Patent number: 8076764
    Abstract: A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: December 13, 2011
    Assignee: Elpida Memory Inc.
    Inventors: Junji Yamada, Hiroaki Ikeda, Kayoko Shibata, Yoshihiko Inoue, Hitoshi Miwa, Tatsuya Ijima
  • Patent number: 8009454
    Abstract: Provided is a resistance random access memory (RRAM) device and a method of manufacturing the same. A resistance random access memory (RRAM) device may include a lower electrode, a first oxide layer on the lower electrode and storing information using two resistance states, a current control layer made of a second oxide on the first oxide layer and an upper electrode on the current control layer.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: August 30, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-jae Lee, Yoon-dong Park, Hyun-sang Hwang, Dong-soo Lee
  • Patent number: 7936039
    Abstract: A pixel for a CMOS photo sensor with increased full well capacity is disclosed. The pixel having a photosensitive element, a photo gate, potential well and a readout circuit. The photosensitive element having a front side and a back side, for releasing charge when light strikes the back side of the photosensitive element. The potential well receives the released charge from the photosensitive element. The photo gate located on the front side of the photosensitive element, for transferring the released charge from the potential well to a sense node. The readout circuit coupled to the sense node, for measuring a voltage corresponding to the released charge transferred to the sense node.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: May 3, 2011
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventor: Stefan Clemens Lauxtermann
  • Patent number: 7923285
    Abstract: A non-volatile memory with a self-aligned RRAM element includes a lower electrode element, generally planar in form, having an inner contact surface; an upper electrode element, spaced from the lower electrode element; a containment structure extends between the upper electrode element and the lower electrode element, with a sidewall spacer element having a generally funnel-shaped central cavity with a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode. A RRAM element extends between the lower electrode element and the upper electrode, occupying at least a portion of the sidewall spacer element central cavity and projecting from the sidewall spacer terminal edge toward and making contact with the lower electrode. In this manner, the spandrel element inner surface is spaced from the RRAM element to define a thermal isolation cell adjacent the RRAM element.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: April 12, 2011
    Assignee: Macronix International, Co. Ltd.
    Inventors: Erh-Kun Lai, ChiaHua Ho, Kuang Yeu Hsieh
  • Patent number: 7923712
    Abstract: A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of the first electrode contacts the phase change element thereby reducing the contact area between the phase change element and the first electrode and thereby increasing the current density through the phase change element and effectively inducing the phase change at lower levels of current and reduced programming power.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: April 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: John Christopher Arnold, Lawrence Alfred Clevenger, Timothy Joseph Dalton, Michael Christopher Gaidis, Louis L. Hsu, Carl John Radens, Keith Kwong Hon Wong, Chih-Chao Yang
  • Patent number: 7915063
    Abstract: A liquid crystal display device includes a plurality of liquid crystal cells on a substrate, a plurality of drive lines extending along first and second directions and connected to the plurality of liquid crystal cells, a plurality of pad lines extending from each of the plurality of drive lines at a first angle from one of the first and second directions, and a plurality of pads extending at the first angle and connected to each of the plurality of pad lines for supplying external drive signals.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: March 29, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Chang Ho Oh, Su Woong Lee
  • Patent number: 7915084
    Abstract: A stacked die chip scale package, in which a stacked die assembly is mounted within a cavity in a module substrate. In some embodiments certain of the die are stacked on a front side of a stacked die assembly substrate, and the stacked die assembly substrate is inverted in the cavity and the substrate is electrically interconnected to a front side of the module substrate; others of the die are stacked on the back side of the stacked die assembly substrate, and are interconnected by wire bonds to the front side of the module substrate. In some embodiments, the cavity is covered by a heat sink, and the stacked die assembly is mounted onto the heat sink. Also, methods for making the module are provided.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: March 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventor: Sungmin Hong
  • Patent number: 7915660
    Abstract: A junction-free NAND flash memory is described, including a substrate, memory cells, source/drain inducing (SDI) gates electrically connected with each other, and a dielectric material layer. The memory cells are disposed on the substrate, wherein each memory cell includes a charge storage layer. Each SDI gate is disposed between two neighboring memory cells. The dielectric material layer is disposed between the memory cells and the SDI gates and between the SDI gates and the substrate.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: March 29, 2011
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Houng-Chi Wei, Shi-Hsien Chen, Hsin-Heng Wang, Shih-Hsiang Lin
  • Patent number: 7915737
    Abstract: A manufacturing technology is provided capable of improving the reliability of a semiconductor module having a via contact connected to an electrode part of a semiconductor component. The semiconductor module includes: a semiconductor component provided with an electrode part on a mounting surface; an insulating layer provided on the mounting surface of the semiconductor component; a wiring layer formed on the insulating layer; a first conductor part which is embedded in the insulating layer and which is in contact with the electrode part; and a second conductor part which is formed in an aperture provided in the insulating layer above the first conductor part and which electrically connects the first conductor part and the wiring layer.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: March 29, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Mayumi Nakasato, Yoshio Okayama, Ryosuke Usui
  • Patent number: 7906800
    Abstract: A semiconductor integrated circuit has a first substrate of a first polarity to which a first substrate potential is given, a second substrate of the first polarity to which a second substrate potential different from the first substrate potential is given, and a third substrate of a second polarity different from the first polarity. The first substrate is insulated from a power source or ground to which a source of a MOSFET formed on the substrate is connected. The third substrate is disposed between the first and second substrates in adjacent relation to the first and second substrates. A circuit element is formed on the third substrate.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: March 15, 2011
    Assignee: Panasonic Corporation
    Inventor: Masaya Sumita
  • Patent number: 7902591
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: March 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka