Abstract: A semiconductor device includes a plurality of repeatable circuit cells connectable to one or more conductors providing at least electrical connection to the circuit cells and/or electrical connection between one or more circuit elements in the cells. Each of the circuit cells are configured having gates and active regions forming a grating, wherein, for a given active layer in the device, a width of each active region is substantially the same relative to one another, a spacing between any two adjacent active regions is substantially the same, a width of each gate is substantially the same relative to one another, and a spacing between any two adjacent gates is substantially the same.

Abstract: One aspect of the present invention is directed to a heterojunction bipolar transistor (HBT) comprising: a substrate; a buffer layer of undoped semiconductor material; a sub-collector layer; a collector layer; a base layer; an emitter layer; a emitter cap layer; and a contact layer; wherein a planar doping sheet is included between the substrate layer and the collector layer; and a collector electrode in electrical connection to said collector layer; a base electrode in electrical connection with said base layer; and an emitter electrode provided in electrical connection to said emitter layer.

Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.

Abstract: A semiconductor device mounting socket is disclosed that is fixed to a motherboard and is used for mounting a surface mounted semiconductor device on the motherboard. The semiconductor device mounting socket includes a bracket that is fixed to the motherboard and a pad pitch converting member that is arranged within the bracket. The pad pitch converting member includes an upper face on which semiconductor device side pads are arranged at a first pitch corresponding to the pitch of pads of the surface mounted semiconductor device, and a lower face on which motherboard side pads that are electrically connected to the semiconductor device side pads are arranged at a second pitch that is different from the first pitch. The surface mounted semiconductor device is arranged above the pad pitch converting member within the bracket.

Abstract: A semiconductor having an ˜5V operational range, including a drain side enhanced gate-overlapped LDD (GOLD) and a source side halo implant region and well implant. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and a very lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a source side of the device and within the high energy well implant. An implant region on a drain side of the lightly doped epitaxial layer forms the gate overlapped LDD (GOLD). A doped region within the halo implant region forms a source. A doped region within the gate overlapped LDD (GOLD) forms a drain. The structure enables the manufacture of a deep submicron (<0.3 ?m) power MOSFET using existing 0.13 ?m process flow without additional masks and processing steps.

Abstract: A method of darkening a defective pixel including a short between a source electrode and a drain electrode in a thin film transistor substrate includes forming a gate line and a data line on a substrate to define a pixel region; forming a thin film transistor at a crossing of the gate line and the data line, the thin film transistor having a gate electrode, a source electrode and a drain electrode; forming a pixel electrode and a common electrode in the pixel region; forming a common line provided in parallel to the gate line and connected to the common electrode; forming an extended part of the drain electrode in parallel to the gate line; and cutting the extended part along a cutting line.

Abstract: A driving circuit of a liquid crystal display, having a plurality integrated circuit chips and a conductive line. The integrated circuit chips are electrically connected to each other via the conductive line, and the impedance between each integrated circuit chip and the conductive wire is different, thereby an input voltage for each integrated circuit chip is substantially the same.

Abstract: This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be set with reduced substrate doping requirements. Current leakage is improved by this process as well.

Abstract: Gate lines and a gate shorting bar connected to the gate lines, which include lower and upper films, are formed on a substrate. A gate insulating layer, semiconductors, and ohmic contacts are formed in sequence. Data lines and a data shorting bar connected to the data lines, which include lower and upper films, are formed thereon. A passivation layer is formed on the data lines and the data shorting bar. The passivation layer and the gate insulating are patterned to form contact holes exposing the lower films of the gate lines and the data lines. Connecting portions of the gate lines and the data lines for connection with driving circuits are locate opposite the shorting bars with respect to the contact holes.

Abstract: A nitride-based compound semiconductor light emitting device has a first ohmic electrode, a first bonding metal layer, a second bonding metal layer and a second ohmic electrode provided in this order on a conductive substrate, and also has a nitride-based compound semiconductor layer provided on the second ohmic electrode. A surface of the second ohmic electrode is exposed.

Abstract: A semiconductor device and a method of manufacturing the same, wherein first and second gate electrodes are formed to have a spacer shape. The length of an underlying dielectric film can be automatically controlled. A gate oxide film and a third gate electrode are formed between the first and second gate electrodes. Voids are not generated when burying the third conductive film. A thickness and width of the gate oxide film can be freely controlled.

Abstract: A memory charge storage node (120.1, 120.2, 120.3) is at least partially located in a trench (124). The memory comprises a transistor including a source/drain region (170) present at a first side (124.1) but not a second side (124.2) of the trench. Before forming conductive material (120.3) providing at least a portion of the charge storage node, a blocking feature (704) is formed adjacent to the second side (124.2) to block the conductive material (120.3). The blocking feature can be dielectric left in the final structure, or can be a sacrificial feature which is removed after the conductive material deposition to make room for dielectric. The blocking features for multiple trenches in a memory array can be patterned using a mask (710) comprising a plurality of straight strips each of which runs through the memory array in the row direction. The charge storage node has a protrusion (120.

Abstract: Upon a deep-hole capacitor fabrication, a hole is formed in an insulator layer, and then a film of a conductive material is formed on the insulator layer and on the whole inner surface of the hole. The film and the insulator layer are exposed to a chemical-mechanical polishing process to form a lower electrodes of the conductive material. A capacitor dielectric on the lower electrode is formed, and then an upper electrode is formed on the capacitor dielectric.

Abstract: A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.

Abstract: In an organic photodiode, in a gap between a transparent anode formed on a glass substrate, and a reflection cathode formed oppositely thereto, a plurality of light receiving parts as layers of light absorbing composition, and partition walls for insulating between transparent anode and reflection cathode and insulating between adjacent light receiving parts are formed. Partition walls are formed by applying an ink solution to transparent anode and an insulating layer covering its periphery, dissolving the insulating layer by an organic solvent contained in the ink solution, and forming a plurality of dissolved holes contacting with transparent anode. The plurality of light receiving parts are formed by filling the plurality of dissolved holes with the light absorbing composition contained in the ink solution.

Abstract: Memory elements including a first electrode and a second electrode. A chalcogenide material layer is between the first and second electrodes and a tin-chalcogenide layer is between the chalcogenide material layer and the second electrode. A selenide layer is between the tin-chalcogenide layer and the chalcogenide material layer. Optionally, a metal layer, for example a silver layer, is between the tin-chalcogenide layer and the second electrode. Methods for forming the memory elements are also provided.

Abstract: A microelectronic component comprising a dielectric layer having an opening and leads extending across the opening is disclosed. The leads have an offset portion. A method of making a microelectronic assembly comprises connecting each of the leads to a contact on a microelectronic element. A semiconductor chip assembly has a microelectronic component with an opening and leads extending across the opening. The leads are connected to contacts on a semiconductor chip and have at least one twisted portion.

Abstract: An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This greatly reduces secondary electron generation, and accordingly reduces the gain of the parasitic PNP bipolar device. The reduced regeneration in turn raises the critical field value, and hence the safe operating area.