Abstract: In a wireless communications system using orthogonal transmit diversity, wherein the orthogonal transmit diversity signal is produced by a transmitter having first and second radio frequency diversity signals for transmitting from first and second transmit diversity antennas, a radio frequency sample signal that represents the sum of the first and second radio frequency diversity signals is produced. The radio frequency sample signal is then down-converted to produce a down-converted signal having first and second components corresponding to the first and second radio frequency diversity signals, respectively. Thereafter, a first time reference of the first radio frequency diversity signal is recovered from the first component. Finally, a characteristic of the second component that is indicative of a difference in delay between the first and second radio frequency diversity signals is measured using the first time reference.

Abstract: A quad oscillator fault-tolerant clock system for a computer complex comprises two clock sources at each of two computer locations, which are coupled by two duplex links. Each clock source supplies its own clock signal to the other clock source at the same location as well as to the clock sources at the other location over one of the duplex links coupling the two locations. Each clock source continually measures the phase difference between its clock signal and each of the other three clock signals. Periodically, the propagation delay for each link is calculated by taking the average of the phase differences measured by the clock sources driving the two ends of that link. These calculated propagation delays are supplied to each individual clock source, which corrects the phase differences measured by it for the propagation delays.

Abstract: A method and apparatus for synchronization of a clock generator, especially a clock generator of a digital telecommunications exchange. When there is a brief outage of the reference frequency, the voltage controlled oscillator of the phase control circuit whose output frequency determines the frequency of the clock generator continues to operate with the control voltage prevailing until then. Upon resumption of the reference frequency, the phase difference between the reference frequency and the output frequency of the oscillator is measured and corrected with the value of the valid phase difference before the loss of the reference frequency. The corrected value is used as the basis for resumed frequency control.

Abstract: A multi-phase PSK modulation apparatus includes a multi-phase PSK modulator and baseband signal modification circuitry which modifies the baseband signal in accordance with modulation frequencies to correct all or a portion of any offset error, amplitude error and orthogonality errors. The baseband signal modification circuitry permits error correction over a wide range of frequencies using a rather simple arrangement. In addition, spurious outputs, volume and cost of the apparatus are reduced.

Abstract: A family of Phase Locked Loop circuits and methods for extraction of a clock signal from a digital data stream, for example as received by a data communication link receiver is taught. The circuits of this invention are particularly advantageous in gigabit rate links where the propagation delay of digital circuits is comparable to the duration of a bit time interval and therefore careful matching of clock extracting and data sampling circuit topology is required. In certain embodiments, a frequency detector is included making the structure suitable for use in situations where there is a large fractional difference between the incoming data rate and the free running frequency of the receiver VCO. Such is the case when both the incoming data rate and the receiver VCO frequency are not controlled by a precision element such as a crystal or a Surface Acoustic Wave device.