Abstract: A pulse shaping circuit for use in a radiation detector. This circuit is adapted for x-ray spectroscopy. The pulse shaping circuit comprises a circuit for converting the output signal from the radiation detector into a step-function waveform, a pseudo-Gaussian filter consisting of a plurality of cascaded filter circuits, an adder circuit, and a gated integrator for integrating the output from the adder circuit. The adder circuit proportionally adds the outputs of each of the plurality of filter circuits in a predetermined manner and sums them up. The pulse shaping circuit achieves a high counting rate and a high resolution.

Abstract: This present invention provides an equalizing cicruit for a sense amplifier comprising a sense amplifier enable signal generation section which receives a sense amplifier equalizing signal and produces a sense amplifier enable signal. An equalizing control section is connected to receive a signal from the sense amplifier enable signal generation section and the sense amplifier equalizing signal. A first and second sense amplifier equalizing signal generation sections are connected to receive an output from the equalizing control section. A third sense amplifier equalizing signal generation section is connected to receive a signal through the second sense amplifier equalizing signal generation section.

Abstract: A segmented waveform generator comprising a plurality of ramp generators whose outputs are coupled to and summed in a summing circuit to provide a waveform having a desired harmonic content or shape. The ramp generators are triggered by the rising and falling edges of trigger pulses to provide symmetrical segmented waveforms.

Abstract: A substrate bias potential generator for biasing a semiconductor substrate to a predetermined potential includes first and second substrate bias generating circuits which operate alternatively according to the potential of the substrate, whereby consumption of power in the substrate bias potential generator is reduced. The alternative operation of the bias generating circuits each activated by a pulse signal train is performed by using a first insulated gate transistor having a gate electrode connected to the semiconductor substrate, a second insulated gate transistor having a gate electrode for receiving the reference potential, an amplifier for differentially amplifying outputs of the first and second insulated gate transistors, an insulated gate transistor for charging an output of the amplifier to a predetermined potential when the amplifier is activated, and a circuit for transmitting the output of the differential amplifier to the first and second bias potential generating circuits.

Abstract: A buffer 6 operating in response to an amplitude level of a clock signal is provided in a semiconductor integrated circuit device such as, a gate array. By selectively applying clock signals of different amplitude corresponding to operation modes, the buffer 6 operates selectively. Therefore, for example, the designation of a test mode can be detected by the buffer 6. As a result, it is not necessary to provide a terminal for externally receiving a test mode signal.

Abstract: A circuit for controlling the duty cycle of a high frequency logic system clock using negative feedback. A high-level buffer used to drive the system clock bus receives the output of a crystal oscillator. The buffer output is sampled by an integrator circuit which produces a voltage level corresponding to the duty cycle of the clock, and this volage level is compared to a reference voltage using an operational amplifier. The op-amp output is applied to the buffer input as negative feedback to alter the bias level at the buffer input in a way as to vary the point in the rising and falling transitions of the crystal oscillator where the threshold of the buffer is crossed. A circuit monitors the clock signal output of a high-level buffer, and determines whether the duty cycle of the crystal oscillator which drives the output buffer should be increased or decreased.

Abstract: A voltage clamping circuit is provided which includes first condutivity type and second conductivity type transistors serially arranged between first and second reference potential terminals. First control means including a first inverter are connected from the common point between the transistors to a control electrode of the first conductivity type transistor, and second control means including a second inverter are connected from the common point between the two transistors to a control electrode of the second conductivity type transistor, with the first and second inverters having different switching points.

Abstract: A transistor output stage including an output transistor having its base coupled to the emitter of a driver transistor is driven into saturation by a current source which is connected to the base of the driver transistor. When a small output current is flowing through the load connected to the collector of the output transistor, the surplus of the current from the current source is drained from the base of the driver transistor to the collector of the output transistor via the collector-emitter path of a limiting transistor having its base connected to the base of the output transistor. This reduces the power dissipation in the driver transistor and improves the power efficiency of the transistor output stage.

Abstract: A low distortion light source comprising a light emitting diode and a compensating diode connected in parallel with respect to a D.C. bias current and in anti-series with respect to an A.C. signal source. The compensating diode is selected to have a forward resistance similar to the forward resistance of the LED. Adjusting the D.C. bias current through the diodes to be approximately equal matches the forward resistance characteristics and substantially reduces the undesired intermodulation products.

Abstract: A first N-channel transistor (M1) and a second N-channel transistor (M2) are cascode connected and the source electrode of the first transistor is connected to the ground; a third P-channel transistor (M3) and a fourth P-channel transistor (M4) are also cascode connected, and the source of the fourth transistor is connected to a supply voltage; the drains of the second and third transistors (M2, M3) are mutually connected to act as output terminal. According to the invention, the absolute values of the threshold voltages of the second and third transistors are lower than the threshold voltages of the first and fourth transistors, and the gates of the first and second transistors are furthermore mutually connected to act as input terminal for a voltage signal, while the gates of said third and fourth transistors are mutually connected to act as input terminal for a bias voltage.

Abstract: A logic gate comprises a bipolar switching transistor and a depletion mode field effect load device. A current independent voltage source and a voltage independent current source are connected in series between an input terminal of the logic gate and a base of the bipolar transistor. The voltage independent current source is a depletion mode field effect transistor having a source and drain which are connected in series with the current independent voltage source and the base of the bipolar transistor. A feedback device is connected in series between a gate of the current source field effect transistor and a gate of the load transistor. A discharge device is connected in parallel with the current independent voltage source for actively discharging a base-emitter junction of the bipolar transistor during switching of the bipolar transistor from an on state to an off state. The logic gate is particularly suitable for use in memory elements.

Abstract: A radiation-hardened temperature-compensated precision voltage reference includes two diodes connected in series having a prescribed operating current (I.sub.B) flowing therethrough. In one embodiment, a first of the two diodes comprises a reversed-biased avalanche diode (32), and a second of the two diodes comprises a forward biased Schottky diode (30). In another embodiment, a reversed biased avalanche diode (42) is connected in series with a reverse biased tunneling diode (40). Both diodes of either embodiment include opposite and offsetting temperature and neutron coefficients of voltage. A method of adjusting the temperature and neutron coefficients of at least one of the two diodes includes selectively adjusting the current density of one of the diodes by selectively trimming the area of the diode dipole.

Abstract: A voltage limiter includes a first FET of a given polarity having the source electrode adapted to be connected to a positive supply terminal. There is a second FET of an opposite polarity to said first and having the source electrode adapted to be connected to a supply terminal which is negative with respect to said positive terminal. The voltage at each terminal may typically vary during operation. There is a voltage clamp means connected between the drain electrodes of said first and second FETs with the gate electrode of the first FET connected to the drain electrode of the second FET and with the gate electrode of the second FET connected to the drain electrode of the first FET, to cause the voltage across said voltage clamping means to remain constant in spite of variations in said positive and negative supplies. The voltage across the drain electrodes of the FETs is further employed as a biasing source for additional logic circuits.

Abstract: A temperature and processing compensated time delay circuit of the type which can be fabricated in a monolithic integrated circuit utilizes a field effect transistor (FET) (12) connected to the terminals of a charged capacitor (14). A bias voltage connected to the gate of the FET (12) varies with temperature in a manner to compensate for the changes in current which flows from the capacitor (14) through the FET (12) due to changes in temperature. The bias voltage also varies from one integrated circuit to another in a manner to compensate for variations in FET threshold voltage caused by variations in the processing of the integrated circuits.

Abstract: A low power, high noise margin logic gate comprises: an input terminal, an output terminal, and first and second voltage supply terminals; an enhancement mode switching FET having a gate connected to the input terminal, a source and a drain; a load device connected between the drain of the switching FET and the first voltage supply terminal; a feedback device connected between the source of the switching FET and the second voltage supply terminal; a two terminal level shift device connected between the drain of the switching FET and the output terminal; and an enhancement mode pulldown FET having a gate connected to the source of the switching FET, a source connected to the second voltage supply terminal, and a drain connected to the output terminal. The logic gate as defined above operates as an invertor.

Abstract: A logarithmic I.F. amplifier having a common input terminal for receiving input signals with the method of construction including a pair of channels connected in a parallel configuration, the first channel being non-attenuated for receiving an input signal at full signal strength while the second channel is attenuated for substantially reducing the power level of the input signal, the construction resulting in saturation of a plurality of successive amplifying stages of the non-attenuated channel with increasing input signal strength prior to the delayed saturation of a plurality of duplicate amplifying stages of the attenuated channel, the attenuated channel continuing to provide compressed output signal data after the saturation of the amplifying stages of the non-attenuated channel, the sum of the output signal data from the pair of channels being effected on a summation line for providing an extended dynamic range of the logarithmic I.F. amplifier.