Patents Examined by T. Dinh
  • Patent number: 11961556
    Abstract: Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: April 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Amitava Majumdar, Radhakrishna Kotti, Rajasekhar Venigalla
  • Patent number: 11957052
    Abstract: According to one embodiment, a thermoelectric material are provided. The thermoelectric material includes a sintered body formed of p-type and n-type thermoelectric materials for the thermoelectric conversion element. The thermoelectric materials have a MgAgAs type crystal structure as a main phase. An area ratio of internal defects of the thermoelectric materials for one thermoelectric conversion element is 10% or less in terms of a total area ratio of defective portions in a scanning surface according to ultrasonic flaw detection in a thickness direction of the thermoelectric material. No defect having a length of 800 ?m or more is present at any vertex of chips of the thermoelectric materials.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: April 9, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Materials Co., Ltd.
    Inventors: Shinichi Yamamoto, Masami Okamura, Nobuaki Nakashima, Masanori Mizobe
  • Patent number: 11955919
    Abstract: An electric motor system includes a battery, an inverter, an electric motor, a zero-phase switching arm and a control unit. The inverter converts DC power output from the battery into three-phase AC power and outputs the three-phase AC power to the electric motor. A rotor of the electric motor rotates by the three-phase AC power output from the inverter. A neural point of the electric motor is connected to the zero-phase switching arm. A zero-phase current flowing through respective windings of the electric motor is adjusted by switching of the zero-phase switching arm. By this means, in the electric motor system, torque is generated at the rotor also using the zero-phase current as well as a three-phase AC current flowing through the respective windings.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: April 9, 2024
    Assignee: DENSO CORPORATION
    Inventors: Makoto Taniguchi, Kazunari Moriya, Kenji Hiramoto, Hideo Nakai, Yuuko Ohtani, Shinya Urata, Masafumi Namba
  • Patent number: 11955913
    Abstract: In one aspect, a movable barrier operator system is provided that includes a motor configured to be coupled to a movable barrier. The motor has a power rating indicative of a minimum power to be supplied to the motor in order for the motor to move the movable barrier. The system further includes an external power supply configured to connect to an electrical outlet. The external power supply has a plurality of outputs each having a power rating indicative of a maximum power the output supplies, the output power rating being less than the motor power rating. The movable barrier operator system includes combiner circuitry configured to combine power from the outputs of the external power supply and provide the combined power to the motor. The system further includes a monitoring circuit configured to detect a fault condition of any of the outputs of the external power supply.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: April 9, 2024
    Assignee: The Chamberlain Group, LLC
    Inventors: Anthony David Bertini, Edwin Fernelly Moreno Hortz, James Scott Murray
  • Patent number: 11955166
    Abstract: Embodiments of the disclosure include signal processing methods to precondition signals for transmission on a high speed bus. A preconditioning circuit is configured to receive a serialized data signal at an input node and to precondition the serialized output data signal to provide a preconditioned output signal at an output node. The pre-conditioning circuit may include a feedback circuit coupled between the input node and the output node that is configured to independently control both of a propagation delay between the output node and the input node and a magnitude of emphasis/de-emphasis applied to a signal at the output node for provision to the input node.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: April 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Atsushi Mamba, Tetsuya Arai, Guangcan Chen
  • Patent number: 11955905
    Abstract: A three-phase/two-phase conversion unit 43 generates a composite vector i?? of three-phase AC currents based on AC currents iu, iv, and iw. An electrical angle calculation unit 44 outputs the electrical angle of the composite vector i?? with reference to the U-phase AC current iu. A quadrant calculation unit 45 obtains which quadrant of the first to sixth quadrants partitioned in advance the acquired electrical angle corresponds to, confirms whether the composite vector i?? passes through the set quadrant, and outputs quadrant information thereof. A failure detection unit 47 determines whether the composite vector i?? has rotated from the first quadrant to the sixth quadrant, and when there is a quadrant that has not been passed, considers that it is a failure state, specifies a failure part of the switching element from the relationship between the electrical angle and the failure part, and outputs failure information to a PWM signal generation unit 42.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: April 9, 2024
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Yasuhiro Ishikawa, Ryohichi Inada
  • Patent number: 11955182
    Abstract: Adaptive and dynamic control of the duration of a pre-program pulse based on a number of planes selected for the pre-program operation is disclosed. A value for a pre-program time increment parameter may be selected based on the number of planes for which the pre-program operation will be performed or determined based on a predefined association with the number of planes. A pre-program voltage pulse may then be applied for a duration that is equal to a default duration for a single-plane pre-program operation incremented by the time increment parameter value. This approach solves the technical problem of Vt downshift for multi-plane pre-program operations, and thus, ensures that the success rate of secure erase operations does not diminish as the number of planes increases. This, in turn, allows for pre-program operations to be consistently performed on a multi-plane basis, which produces the technical effect of improved system performance.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: April 9, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Long Pham, Sai Gautham Thoppa
  • Patent number: 11948640
    Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: April 2, 2024
    Assignee: Kioxia Corporation
    Inventors: Makoto Iwai, Hiroshi Nakamura
  • Patent number: 11947222
    Abstract: An electronic device is provided. The electronic device includes a first substrate having a peripheral area, a first inorganic layer disposed on the first substrate, an insulating layer disposed on the first inorganic layer and formed a recess, and a second inorganic layer disposed on the insulating layer and formed in the recess. The recess is disposed in the peripheral area. A thickness of the second inorganic layer is less than a thickness of the insulating layer.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: April 2, 2024
    Assignee: Innolux Corporation
    Inventors: Fiona Jhan, Lavender Cheng
  • Patent number: 11950366
    Abstract: An electronic component mounting structure is an electronic component mounting structure in which an electronic component group is mounted on a substrate, and a pattern constituting a part of a current path between the inflow port and the outflow port, the electronic component group includes a plurality of electronic components connected between the inflow port and the outflow port, each of the electronic components has a current inflow terminal electrically connected to the inflow port and a current outflow terminal electrically connected to the outflow port, and one of a first spatial distance group and a second spatial distance group has equal spatial distances within the one spatial distance group, and the first spatial distance group includes spatial distances between the inflow port and the inflow terminals, and the second spatial distance group includes spatial distances between the outflow port and the outflow terminals.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: April 2, 2024
    Assignee: TDK CORPORATION
    Inventors: Kazuhiro Hagita, Yoshiaki Ishikawa, Masaharu Moritsugu
  • Patent number: 11948825
    Abstract: A wafer placement table includes: an electrostatic chuck that is a ceramic sintered body in which an electrode for electrostatic adsorption is embedded; a cooling member which is bonded to a surface on an opposite side of a wafer placement surface of the electrostatic chuck, and cools the electrostatic chuck; a hole for power supply terminal, the hole penetrating the cooling member in a thickness direction; and a power supply terminal which is bonded to the electrode for electrostatic adsorption from the surface on the opposite side of the wafer placement surface of the electrostatic chuck, and is inserted in the hole for power supply terminal. The outer peripheral surface of a portion of the power supply terminal is covered with an insulating thin film that is formed by coating of an insulating material, the portion being inserted in the hole for power supply terminal.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: April 2, 2024
    Assignee: NGK INSULATORS, LTD.
    Inventors: Kenichiro Aikawa, Hiroshi Takebayashi, Tatsuya Kuno
  • Patent number: 11945080
    Abstract: A power tool may include an end effector configured to enable a fastener to be applied by the power tool via a fastening cycle, a power unit, a drive assembly configured to apply drive power to the end effector responsive to application of input power thereto, and a motor configured to supply the input power to the drive assembly selectively based on operation of a power control assembly that controls coupling of the motor to the power unit. The drive assembly includes a clutch configured to interrupt application of the drive power at a target torque. The power control assembly may be configured to adaptively change speed of the motor in response to the power tool reaching a predefined torque value that is less than the target torque during the fastening cycle.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: April 2, 2024
    Assignee: APEX BRANDS, INC.
    Inventor: William Carlos Cain
  • Patent number: 11949359
    Abstract: Disclosed embodiments include a system and method of acquiring operating parameter data of a motor system that includes an electric motor. The motor system may be provided as a component of a fan. An embodiment includes recording states of operating parameters during operation of the motor system, wherein the operating parameters include a basic parameter and at least one additional parameter; determining a state-change event of the basic parameter based on a recorded state of the basic parameter; recording a state of the additional parameter upon detection of the state-change event of the basic parameter; linking the recorded state of the additional parameter to the detected state-change event; and storing the recorded state of the additional parameter linked to the detected state-change event.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 2, 2024
    Assignee: ZIEHL-ABEGG SE
    Inventors: Matthias Carsten Kammerer, Bjoern Wenger
  • Patent number: 11942564
    Abstract: A tandem photovoltaic device includes: a tunnel junction between an upper cell unit and a lower cell unit. The lower cell unit is a crystalline silicon cell. The tunnel junction includes: a carrier transport layer, a crystalline silicon layer, and an intermediate layer located between the carrier transport layer and the crystalline silicon layer. The carrier transport layer is a metal oxide layer. The intermediate layer includes a tunneling layer. The crystalline silicon layer has a doping concentration greater than or equal to 1017 cm?3. The carrier transport layer is in direct contact with a shadow surface of the upper cell unit. If the crystalline silicon layer is a p-type crystalline silicon layer, a first energy level is close to a second energy level. If the crystalline silicon layer is an n-type crystalline silicon layer, a third energy level is close to a fourth energy level.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: March 26, 2024
    Assignee: LONGI GREEN ENERGY TECHNOLOGY CO., LTD.
    Inventors: Zhao Wu, Chen Xu, Zifeng Li
  • Patent number: 11942145
    Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chuan Yang, Jui-Wen Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 11942260
    Abstract: A power module includes a power circuit and a magnetic assembly. The power circuit includes at least one switch element. The magnetic assembly includes at least one first electrical conductor and a magnetic core module comprising at least one hole, wherein the at least one first electrical conductor passes through the at least one hole, and a terminal of the at least one first electrical conductor is electrically connected to the at least one switch element. The power circuit and the magnetic assembly are arranged in sequence along a same direction.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: March 26, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yahong Xiong, Da Jin, Qinghua Su
  • Patent number: 11942395
    Abstract: An apparatus including first and second substrates. The first and second substrates each include a base and at least one peripheral wall extending from the base. One of the at least one peripheral walls of the first or second substrates includes at least one well, and the other of the at least one peripheral walls of the first or the seconds substrate that does not include a well is mechanically anchored to the well. The apparatus includes a stack having a first and second end, and the stack is disposed on the base of the first and/or the second substrates at the first and/or second ends. The stack includes at least one element configured to generate energy. A method of assembling the apparatus by contacting the substrates.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: March 26, 2024
    Assignee: Ciena Corporation
    Inventors: Raphael Beaupré-Laflamme, Simon Savard, Lam Nguyen
  • Patent number: 11942334
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the second thickness is different from the first thickness. In some embodiments, the first conductive trace and the second conductive trace have rectangular cross-sections.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Jeremy Ecton, Aleksandar Aleksov, Suddhasattwa Nad, Kristof Kuwawi Darmawikarta, Vahidreza Parichehreh, Veronica Aleman Strong, Xiaoying Guo
  • Patent number: 11942155
    Abstract: A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a first programming transistor, a second programming transistor, a first reading transistor coupled to the first programming transistor in series, and a second reading transistor coupled to the second programming transistor in series. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells. The logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first programming transistor or second programming transistor.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yih Wang
  • Patent number: 11935579
    Abstract: A protection circuit can be applied in a chip, and include: a first protection unit and a first element to be protected, wherein the first protection unit is configured to receive a first input signal and a control signal, and is configured to output a first output signal, the first element to be protected includes a first P-type transistor, and a gate of the P-type transistor is configured to receive the first output signal. When the chip enters a burn-in test, the first output signal is a high-level signal.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: March 19, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Geyan Liu, Yinchuan Gu