Abstract: A first location and a last location of the required part of a first piece of picture information displayed at a display part are specified by cursors. Cleared data is transferred to a picture element memory where said picture information is stored for removing unnecessary picture information. The extracted necessary picture information is recorded in a magnetic tape device. Only the necessary part of a second piece of picture information is extracted in a similar manner and is recorded in the magnetic tape device. A logic sum of a title input from the keyboard and said first piece of picture information is obtained for each scanning line to provide a first synthesized picture. A logic sum of the first synthesized picture and said second piece of picture information is obtained for each line to provide a second synthesized picture.

Abstract: A load management terminal is utilized as an end device in a utility's distribution network communication system. The distribution network carries electrical power as well as communication signals. The load management terminal is comprised of a power line coupling unit for connecting the load management terminal to the power distribution network. A signal receiver and conditioning unit produces a command signal in response to a received communication signal. A solid state memory contains preprogrammed instructions and data. A control logic circuit performs load control functions in response to the preprogrammed instructions, data and the command signal. These load control functions include the opening and closing of load control switches for selectively disconnecting and connecting, respectively, customer loads. A cold load pick-up produces power outage information enabling the load management terminal to provide local, load control functions.

Abstract: In a parallel data processing system architecture capable of processing in parallel a plurality of data elements from a linear vector stored in a memory module array having in number a power-of-two memory modules, a high degree of conflict-free access to the stored linear vector data elements is achieved through skewed storage wherein a skewing occurs at every Mth address and a further skewing at every M.sup.2 address wherein M (a power-of-two) is equal to the number of memory modules. The data elements are fetched through a connection network for processing in a processor array having in number a power-of-two processors.

Abstract: A microprogram sequencer for generating in a proper sequence the addresses of the successive microinstructions used in executing a given machine instruction includes a PROM next address generator that produces the successive addresses. The successive addresses are utilized as the successive microinstructions. Each address produced includes a normal next address, but this normal next address may be alterable by address alteration signals that are generated in response to a number of sensed conditions within the computer and in response to predetermined machine instruction register bits. The address alteration of a normal next address, if required, is accomplished within the same clock period in which the normal next address is initially formed, permitting jump or branch instructions to be performed as rapidly as normal instructions. No mapping PROM, microsequencer counter, nor microsequencer incrementer are needed to implement the present invention.