Abstract: A phase detector is disclosed that eliminates frequency ripple in a phase-locked loop circuit. The detector includes first and second circuits for providing UP and DOWN signals respectively. It also includes a delay element for setting the duration of the DOWN signal so as to eliminate phase jitter and static phase offset.

Abstract: A device and method for self-timed, temporary disabling or latching of an electric circuit. A first portion of the circuit has sensing means for sensing a change in the value of an output signal of a second circuit portion corresponding to a change between logic states. The first circuit portion also includes immobilizing means responsive to the sensing means for temporarily disabling or latching the second circuit portion. The immobilizing means functions after such a change in logic state has occurred and, in addition, when the output signal of the second circuit portion has acquired a value corresponding to a predetermined logic state. Disabling occurs when the immobilizing means turns off a switch of the second portion. Latching occurs when the immobilizing means activates latch means of the second portion, thereby fixing voltage level(s) and corresponding logic state(s).

Abstract: The present invention ensures that the entire data path of the synchronous integrated circuit device composed of master and slave latches is initialized upon power-up in a test mode, thereby overcoming a prior art problem of non-initialization of the device data path. In the test mode, the master clock signal is initialized internally to the synchronous integrated circuit device to allow the master latch to conduct. A clock signal which is a derivative of a master clock signal is controlled to be equal to a first logic state in order to control a slave latch element of the synchronous integrated circuit device to conduct, regardless of the state of the master clock signal. Controlling the clock signal to be equal to the first logic state allows the clock signal to be able to control the slave latch element so that entire data path of the integrated circuit device is initialized upon power-up of the device in the test mode.

Abstract: The circuit for clock signal extraction from a high speed data stream which allows a rapid attainment of the identity between the frequencies of the locally generated clock signal and of the data signal, even when such frequencies are very different. The circuit can easily be inserted into a more complex CMOS digital integrated circuit, it has low power dissipation and is capable of operating at bit rates exceeding 300 Mbit/s. The circuit has a main phase locked loop, which controls a voltage controlled oscillator by continually controlling its phase and a secondary loop, which allows the main loop to become locked, by causing the voltage controlled oscillator to oscillate at a frequency close to the operating frequency.

Abstract: A voltage stepup circuit having a plurality of setup circuit units connected in stages between an input voltage node and a stepup voltage node. Each circuit unit comprises at least two first and second MOS transistor T1 and T2. Each of first stepup capacitors is connected between a first clock signal supply node and a first connection node at which the drain and gate of a corresponding one of odd-numbered MOS transistors, of a plurality of MOS transistors connected in series through the plurality of stepup circuit units, are connected together. Each of second stepup capacitors is connected between a second connection node at which the drain and gate of a corresponding one of even-numbered MOS transistors of the plurality of MOS transistors connected together and a second clock signal supply node for supplying said second connection node with a second clock signal whose pulse width does not overlap in time with that of the first clock signal.

Abstract: A vanity mirror including: a mirror body arranged with a mirror; a cover turnably received by the mirror body so that it may be opened/closed relative to the mirror; and spring means for urging the cover in at least the closing direction. A shaft is fixedly received by one of the mirror body and the cover for receiving the other and is formed with a friction surface part having an enlarged coefficient of friction on the surface to be brought into sliding contact with the other.

Abstract: Addition is performed by a capacitive coupling or resistive coupling. A quantizing circuit is realized by plurality of thresholding circuits receiving an analog input voltages. Subtraction is performed by to MOSs of anti-polarity inputted analog input voltages to gates.

Abstract: A method and circuitry are provided for latching information. The information is selectively transferred from a selected one of: a first node (DIN) to a second node (416); and a third node (SIN) to a fourth node (419a-b). The transferred information is selectively latched by coupling the second node (416) to the fourth node (419a-b) in response to a signal (308, 410).

Abstract: A BiCMOS circuit includes a CMOS circuit for inverting data applied to an input terminal and a first bipolar transistor, having a base connected to an output point of this CMOS circuit, a collector connected to a power supply voltage and an emitter connected to an output terminal, for charging the output terminal. The BiCMOS circuit also includes a second bipolar transistor, having a collector connected to the output terminal, for discharging the output terminal, a first MOS transistor of a first conductivity type connected in parallel between the base and the collector of the second bipolar transistor and a second MOS transistor of the first conductivity type connected in series with the first MOS transistor and having a gate connected to an output point of the CMOS circuit.

Abstract: A series clock deskewing apparatus uses a series terminated single transmission line system to deliver a clock signal to a load. A plurality of series clock deskewing apparatuses are implemented, one for each load, so that the clock signal is delivered to all loads simultaneously. Each series clock deskewing apparatus has a single series termination resistor with the same impedance value as the transmission line to which it is coupled. For each load, the clock signal travels the transmission line from a clock generator to the load and is simultaneously applied to the deskewing apparatus. A clock signal is reflected at the load back to the deskewing apparatus. The roundtrip transit time is determined by the deskewing apparatus which causes an appropriate delay to adjust each clock signal to arrive synchronously at all the loads.

Abstract: A phase detector is disclosed that eliminates frequency ripple in a phase-locked loop circuit. The detector includes first and second circuits for providing UP and DOWN signals respectively. It also includes a delay element for setting the duration of the DOWN signal so as to eliminate phase jitter and static phase offset.

Abstract: A power semiconductor device (4) has a main current carrying section (4a) with a number of parallel-connected active device cells (5) and a first main electrode (6) coupled to a first terminal (2), a second main electrode (7) connected to a second terminal (3) and a control electrode (8) and a sense current carrying section (4b) with at least one sense cell (5a) similar to the active device cells (5) and having a first main electrode (6) coupled to the first terminals (2) and a second main electrode (9). A current sensing arrangement (10) has a first resistor (R1) coupling the second main electrode (9) of the sense current carrying section (4b) to the second terminal (3), a second resistor (R2) similar to the first resistor (R1) and a current source (11) coupled in series with the second resistor to the second terminal (3) for supplying a reference current (Ir) through the second resistor (R2).

Abstract: A circuit technique for implementing programmable zeros in high speed CMOS filters is disclosed. The circuit uses both PMOS and NMOS type transconductance elements to implement a biquad with a real zero and two complex poles. The NMOS transconductance element is biased by the total bias current required by several PMOS transconductance elements and can thus provide larger transconductance as required by the equalization function. Programmability is achieved by dividing the NMOS transconductance elements into a plurality of identical sub-elements that are connected in parallel via digitally programmable switches.

Abstract: Digital signal delay lines with electrically programmable and trimmable delay times, including electrically erasable and reprogrammable delay times. Floating gate field effect transistors are programmed to select current, capacitance, and/or threshold and thereby set a delay time determined by acurrent charging of a capacitor up to a threshold voltage. Trimming after packaging avoids package offsets. Temperature and power supply voltage compensation by current combining gives compensation compatible with the electrical programming.

Abstract: A method of setting the polarity of a digital signal coming from a first integrated circuit, said digital signal being representative of data generated within the integrated circuit and requiring application to an input of a second integrated circuit that requires a predetermined polarity. The method comprises storing the required polarity externally to said first integrated circuit at its digital signal output, an acquisition sequence for acquiring the stored polarity while the data is inactive, and an application sequence for applying the acquired polarity to the information when active in order to generate on an output of said first integrated circuit the digital signal for application to the input of said second integrated circuit. The method is applicable in digital systems that include integrated circuits that may come from different sources.

Abstract: A microscope includes a revolver on which are mounted at least three objective lenses having different magnifications, a driving device for revolving the revolver to switch the objective lens disposed in an optical path of the microscope, an operating device capable of giving a plurality of drive commands for disposing a desired objective lens in the optical path of the microscope to the driving device and an invalidating element for invalidating a specified drive command among the drive commands. The specified drive command serves to switch the objective lens disposed in the optical path of the microscope from a first objective lens having a minimum magnification to a second objective lens having a maximum magnification among the objective lenses.

Abstract: First and second phase synchronization circuits include variable frequency oscillation circuits of the same structure. Operating point shift is performed by an operating point shift circuit, the output Vg of which is then inputted into an addition circuit. The oscillation frequency of the variable frequency oscillation circuits is con, rolled by the output Vf2 of the addition circuit. The signal Vf2 is also inputted into the terminal IN of a variable frequency oscillation circuit in a one-shot pulse generating circuit. The one-shot pulse width is determined by the signal Vf2 with the counts m of an edge detecting circuit. The one-shot pulse OS is inputted into a third phase synchronization circuit which in turn provides SYCLK and SYDT through a data standardizing circuit.

Abstract: A scan cell is described which can function as either a positive edge triggered latch or a double edge triggered latch during normal functional operation of circuitry to be scan tested. It functions only as a positive edge triggered latch when scan testing of a logic structure is to be performed.

Abstract: AC coupling is effected by a feedback circuit that detects a DC component in the coupled signal, and adjusts a DC subtraction signal accordingly. In one embodiment, a digital signal processor (DSP) analyzes the coupled signal for a remaining DC component, and controls the subtraction signal. Use of a DSP allows dynamic control of parameters including AC cutoff frequency, gain, and transfer function. Another embodiment provides accurately phase matched AC coupling across two or more signal channels.

Abstract: The present invention utilizes a CMOS (complementary metal-oxide-semiconductor) inverter, which includes a PMOS transistor and an NMOS transistor connected in cascade, and back-gate biasing circuits. The back-gate biasing circuit consists of capacitors and loads (active load or passive load). By providing a bias voltage to either one of bulks of the transistors or both of them, the constituted CMOS inverter demonstrates higher operation speed and lower standby current than the conventional one.