Patents Examined by T Lan
  • Patent number: 6522993
    Abstract: A method is provided for evaluating and marking deviations of a surface of a part from a design standard for the surface. The method comprises determining a point deviation for each of a plurality of points on the surface and determining deviation regions for the surface. Each deviation region includes only surface points having point deviations within a predefined deviation range associated with the deviation region. The method further comprises preparing a graphical representation of the surface illustrating the deviation regions and applying a copy of the graphical representation to the surface.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: February 18, 2003
    Assignee: General Electric Company
    Inventor: Andrew John Tomko
  • Patent number: 5947290
    Abstract: A packaging member comprises a base member and a pair of side members hingedly attached to opposite sides of the base member such that the side members can be alternatively and selectively disposed in two different positions with respect to the base member. In particular, the side members can be disposed perpendicular to the base member, or alternatively the side members can be disposed at predetermined angled positions with respect to the base member. When disposed perpendicularly to the base member, the packaging member has a substantially U-shaped configuration enabling the packaging member to serve as an edge protector, whereas when the side members are disposed at their angled positions with respect to the base member, the packaging member has a substantially trapezoidal configuration enabling stacking or nesting of the packaging member along with other similar packaging members so as to optimize storage, shipping, and handling or transportation costs.
    Type: Grant
    Filed: July 20, 1998
    Date of Patent: September 7, 1999
    Assignee: Illinois Tool Works Inc.
    Inventor: Michael D. Loeschen
  • Patent number: 5926053
    Abstract: A processing system includes circuitry and methodology for selecting clock generation modes between phase-locked loop and static delay line loop circuitries. The node may be selectable through an externally accessible pin, an internal bond wire option, a boundary test scan control point, or other programmable register or control point.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: July 20, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Mark W. McDermott, Antone L. Fourcroy
  • Patent number: 5915564
    Abstract: A single-piece cardboard sheet into which slots and tabs are strategically cut to permit its folding into a carton for packaging a spur. The top section of the unfolded cardboard carton contains a cutout and an elongated tab projecting upwards; the end of the tab consists of a distal foldable flap separated from the tab by two lateral indentations. The central section of the carton contains a hanging slot suitable for receiving a hook of a display rack and two lower vertical slots spaced apart a distance commensurate with the size of the spur. In addition, a partial cut in the area above and around the upper slot defines a boundary between the upper and central sections of the carton such that the hanging slot is unencumbered when the two sections are folded. Finally, a horizontal slit sized to receive the tab is cut above and between the two vertical slots, the exact position being selected to meet the tab when the upper section of the carton is folded over the central section.
    Type: Grant
    Filed: October 7, 1997
    Date of Patent: June 29, 1999
    Assignee: Eastwest International (Taiwan) Enterprises
    Inventor: Chang Hsi-Chang