Abstract: A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the second conductive structure is interposed between the first and third conductive structures. A first dielectric is formed over these conductive structures, then a portion of the first dielectric layer is removed which forms a hole in the dielectric layer to expose the second conductive structure. Subsequently, the second conductive structure is removed to leave a void or tunnel in the dielectric layer where the second conductive structure had previously existed. Finally, a second dielectric layer is provided to fill the hole but to leave the void or tunnel in the dielectric layer subsequent to the formation of the second dielectric layer. An inventive structure resulting from the inventive method is also described.

Abstract: A method of reducing the computer calculation time of a superposition is disclosed. A computing device having an input unit, an output unit, a memory unit, and an operation unit, is used to calculate the model superposing the function with shifted value of the variable. The model operator is formed by superposing a delta function in the same manner as the superposition of the function. The convolution of a model operator and the function is determined to thereby reduce the calculation time of the model superposing the function with the shifted value of the variable.

Abstract: The present invention provides a method and apparatus for determining the RC delays associated with branches of a network comprised in an integrated circuit. The apparatus comprises logic configured to execute a rules checker algorithm. When the rules checker algorithm is executed, the algorithm analyzes information relating to the network and determines the total effective RC delays between the output of a driver gate of the network and the inputs of one or more receiver gates of the network.

Abstract: A method for manufacturing a semiconductor device that fills contact holes with conductive material such as aluminum or an aluminum alloy. A semiconductor device is manufactured by the process of forming an opening such as a contact hole in an interlayer dielectric film formed on a semiconductor substrate having a device element formed thereon. A first film and a second film made of conductive material such as aluminum or an alloy containing aluminum are formed on the interlayer dielectric film and the opening. The second film is then gradually cooled.

Abstract: A metallization structure and method for fabricating such a metallization structure are presented. The present method preferably includes forming a void within a metal layer. The void may have a void pressure level, which is preferably approximately equal to the pressure in a deposition chamber in which the metal layer is arranged when the void is formed. Subsequently, the void may be collapsed by increasing a pressure level outside of the void to a collapsing pressure level significantly above the void pressure level. Increasing a pressure level outside of the void preferably includes increasing a pressure level within the deposition chamber to a collapsing pressure sufficient to collapse the void. A metallization structure formed by such a process may be substantially void-free, even in narrow, high aspect ratio metallization cavities.

Abstract: An objective of this invention is to provide a process for manufacturing a shared contact without protrusion toward an adjacent gate electrode and an improved shared contact. This invention allows a shared contact without protrusion from the gate electrode to be prepared by removing a gate electrode which is in contact with a dopant diffusion layer but is not used as a transistor element and forming a shared contact in the area. As a result, a cell size is larger in an SRAM according to this invention than in that according to the prior art.

Abstract: A process for forming a dual damascene cavity in a dielectric, particularly a low k organic dielectric, is described. The dielectric is composed of two layers separated by an etch stop layer. Formation of the damascene cavity is achieved by using a hard mask that is made up of two layers of silicon oxynitride separated by layer of silicon oxide. For both the trench first and via first approaches, the first cavity is formed using only the upper silicon oxynitride layer as the mask. Thus, when the second portion is patterned, little or no misalignment occurs because said upper layer is relatively thin. Additional etching steps result in a cavity and trench part that extend as far as the etch stop layer located between the dielectric layers. Final removal of photoresist occurs with a hard mask still in place so no damage to the organic dielectric occurs. A final etch step then completes the process.

Abstract: A new method of metallization using a three-dimensional aluminum reservoir to increase the electromigration lifetime of a tungsten plug in the fabrication of integrated circuits is achieved. An insulating layer is provided covering semiconductor device structures in and on a semiconductor substrate. Aluminum lines are formed over the insulating layer. An intermetal dielectric layer is deposited overlying the aluminum lines. Via openings are made through the intermetal dielectric layer to the aluminum lines. Aluminum is selectively deposited into the via openings to form aluminum reservoirs in the bottom of the via openings wherein the aluminum does not completely fill the via openings.

Abstract: An electronic tag has a processor, a readable memory for holding an identification number connected to the processor, and an antenna connected to the processor for radiofrequency broadcasting of the identification number. A power supply powers the antenna to broadcast the identification number.A user selectively controls operation or non-operation of the electronic tag by switching an interconnect switch on or off. The interconnect switch permits interconnects the processor, readable memory, antenna, and power supply to selectively allow radiofrequency broadcasting of the identification number. Bitwise communication to a tag reader using only a passive electronic tag is possible.