Abstract: The changed state of a shape of a transformable element of each part is preregistered to a library in an assembly simulation. When two parts collide with each other, the changed state of the element is selected according to an interference condition such as a material, a direction in which force is applied, etc., and the interference between parts is verified based on the selected shape after being changed.

Abstract: A coupled real-time GPS/IMU simulation method with differential GPS includes the steps of receiving real-time trajectory data from a 6DOF trajectory generator and generating GPS simulated measurements (rover and reference) and inertial measurement unit simulated electronic signals based on the real GPS models and IMU models, respectively, and injecting those simulated data into an on-board integrated GPS/INS (global positioning system/inertial navigation system). Therefore, the coupled real-time GPS/IMU simulation method with differential GPS can be applied to evaluate the performance of the integrated GPS/INS in the area of high accuracy positioning in addition to the regular evaluation (one receiver mode).

Abstract: A method for manufacturing a surface acoustic wave apparatus decreases a specific resistance of an electrode film by removing hydrogen occluded in the electrode film that is primarily composed of tantalum, so that the device properties are stabilized. An electrode film primarily composed of tantalum is formed on a piezoelectric substrate. Subsequently, this electrode film is heat-treated in a vacuum at a temperature of about 200° C. to about 700° C. for several hours. Thereafter, the electrode film is patterned so as to produce an interdigital electrode transducer.

Abstract: A method and apparatus for simulated error injection for processor deconfiguration design verification is provided. A simulated error condition request is received from a user through software, such as the operating system executing in the multiprocessor data processing system. In response to the requested simulated error condition, an error condition is injected into a processor of the multiprocessor data processing system via instruction execution. In response to the detection of the error condition and execution of error-path code, a processor is deconfigured. The error condition may be injected by executing an instruction to set an error condition bit in an error condition register.

Abstract: A method for forming an actuating variable to be output periodically by a control unit in output periods for controlling an apparatus, in particular the ignition or fuel injection of internal combustion engines, includes reading output signals of at least two sensors into the control unit and ascertaining individual components of the actuating variable based on the output signals. The sensor output signals are read-in and the individual components are determined periodically at intervals of one read-in period or one determination period being equal to or a multiple of the output period of the actuating variable. The read-in period of a sensor output signal is dependent on a speed of variation of the sensor output signal, and in particular it increases as the maximum speed of variation of the sensor output signal decreases. The determination period of each individual component is dependent on the read-in periods of the sensor output signals involved in each individual component.

Abstract: A cup shaped yoke made of sheet material has an opening portion provided in a side wall on an axial end side, a shoulder portion provided in the sidewall on another axial end side, a magnet installation portion for installing a magnet, which is provided in the side wall between the opening and shoulder portions and whose wall thickness is substantially equal to thickness of the sheet material, and a bottom portion, which is provided in a bottom wall, having a boss shaped bearing accommodating portion in a center thereof. Each wall thickness of the opening, shoulder and bottom portions including the boss shaped bearing accommodating portion is equal to or smaller than a half of wall thickness of the magnet installation portion.

Abstract: The present invention provides an electronic component mounting apparatus which can reduce a consumption power amount in comparison with the background art, and a power supply control method which is executed by the electronic component mounting apparatus. A drive power source and a control power source are separately connected and shut-off in accordance with a command from a control device to each of component feed drive parts for driving component feed devices, a component transfer drive device for driving a component transfer device, and a circuit board positioning drive device for driving a circuit board positioning device. The control device detects an individual occurrence of halt condition of each of constitution parts of an electronic component mounting apparatus and shuts off the drive power source to the drive device in the halt condition. Thus, a wasteful power consumption is eliminated and the production is continued with a necessary minimum power.

Abstract: A method of manufacturing the same in an accurate and stable manner, in which a magnetic path length of a thin film coil is shortened by decrease a distance between adjacent coil windings of at least one layer thin film coil. On a first magnetic layer 37, is formed an insulating layer 38, and then a first thin film coil half 40 is formed on the surface of the insulating layer such that a distance between successive coil windings is large. Then, a second thin film coil half 44 is formed such that its coil windings situate between successive coil windings of the first thin film coil half. First and second coil halves 47 and 48 of a second layer thin film coil are formed on the first layer thin film coil in a similar manner. After forming an insulating layer 52, a second magnetic layer 53 and overcoat layer 54 are formed.

Abstract: An improved system, method and software program is provided for facilitating the use of components running in a computer network. The improvement provides virtual replication of a distributed directory in a computer system. The system includes at least two servers, each including a processor connected to a network for store, among other things, a partition of information. The partition may be distributed across the network. The memory of the second server can store, among other things, a virtual replica of the partition. The virtual replica includes a filtered view, or subset, of the information in the partition.

Abstract: Bayesian principal component analysis. In one embodiment, a computer-implemented method for performing Bayesian PCA including inputting a data model; receiving a prior distribution of the data model; determining a posterior distribution; generating output data based on the posterior distribution (such as, a data model, a plurality of principal components, and/or a distribution); and, outputting the output data. In another embodiment, a computer-implemented method including inputting a mixture of a plurality of data spaces; determining a maximum number of principal components for each of the data spaces within the mixture; and, outputting the maximum number of principal components for each of the data spaces within the mixture.

Abstract: A method and an apparatus make available uncommitted register values during the random code generation process. When there is a need for a register to contain a specific (desirable) value, then the register value is committed to that value at that point. Uncommitted values can propagate through one or more previous instructions. All registers and memory begin the test program in the uncommitted state. When the random code generators is done generating the test program, if any uncommitted values remain, then the uncommitted values are committed to arbitrary values.

Abstract: The present invention is directed to a simulation testbench 10 which includes a circuit under test 14 and a plurality of test models 12 designated 1 through N. The test models 12 include at least one of a driver and a monitor. The drivers selectively apply stimuli to the circuit under test 14, and the monitors observe responses to the stimuli from the circuit under test 14. A single controller 16 is provided for the plurality of test models 12. The controller 16 has an instruction source 18 including a list of commands which control the plurality of test models 12. The commands are routed from the instruction source 18 over a model control bus 24 to the plurality of test models 12.

Abstract: The system and method of the present invention is embodied in a multi-state on-chip logic analyzer that is preferably integrated into a VLSI circuit. In general, the logic analyzer is preferably coupled to a multilevel trace array for storing event trace data generated by the logic analyzer. Input and output logic coupled to both the trace array and the logic analyzer allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. The logic analyzer has the capability match one or more programmable trigger events to satisfy one or more programmable conditions. Further, the logic analyzer preferably has the capability to initialize programmable conditions in desired states, and to store event trace data in an on-chip array for trace data reconstruction and analysis.

Abstract: A system includes a unit for dividing a model in mesh units; a unit for generating and displaying a child edge as a new edge from a parent edge obtained by dividing the model in mesh units; a unit for amending the displayed child edge into an optional form; a unit for obtaining correspondence between the parent edge and the amended child edge; and a unit for analyzing structure of an amended model form determined based on the obtained correspondence. With the configuration, a structural analysis can be quickly performed in a simple operation by dividing a model into mesh units, specifying a child edge of an optional curve in a parent edge, projecting the parent edge into the child edge, automatically computing the coordinates, and obtaining the optimum solution in a structural analysis based on the computation.

Abstract: A method for controlling I/O in a multi-processor environment, comprising the steps of: determining if an I/O instruction requiring an interrupt is being executed by one of the processors in the multi-processor environment to transfer data or a command between the processor and an I/O device; performing an interrupt if such an I/O instruction is detected; determining which of the processors in the multi-processor environment is executing an I/O instruction; if only one of the processors is executing an I/O instruction, setting a Last Processor indicator designating that one processor as the processor executing the I/O instruction; and transferring data or a command between the processor designated in the Last Processor indicator and the I/O device in response to the I/O instruction.

Abstract: The present invention includes simulation system devices and methods. The invention can be used to collect information describing a desired data exchange between simulated devices and can assist in the generation of simulation model control programs that implement the desired data exchange. The disclosed methods feature generating simulation control code by interacting with a user to receive an address constraint and by generating a collection of data transfer instructions. Each data transfer instruction includes a data transfer address selected from a collection of addresses. The disclosed systems feature a simplified simulation data entry system including means for receiving address constraint information delimiting a collection of data transfer address values and means for generating a collection of simulation data transfer instructions. Each data transfer instruction may include an address selected from the collection of data transfer address values.

Abstract: An electronic device includes an operation processing unit, a main storage unit, a program storing ROM for storing a plurality of divided program codes and for storing loading program codes for loading the program codes to the main storage unit, an information table storing ROM for storing an information table having a description of information about the program codes to be loaded from the program storing ROM to the main storage unit, and a map management element having a description of virtual addresses in the main storage unit at which the program codes stored in the program storage element are mapped. As a result of this construction, only those program codes requiring quick response are loaded without loading all the program codes to the main storage unit and executed promptly, and thus the system activation time can be reduced.

Abstract: The present invention provides a method and apparatus for evaluating nodes in an integrated circuit to determine whether or not networks containing the nodes meet certain design criteria. The method and apparatus of the present invention are embodied in a rules checking system which evaluates the nodes in the integrated circuit to determine whether or not the networks in the integrated circuit comply with the design rules. Compliance with any particular rule is verified by performing one or more checks on the particular node being evaluated. Some checks require less time to perform than others. In some cases, the result of a single check can provide a determination as to whether or not the network containing the node being evaluated complies with the rule associated with the particular check. Furthermore, some checks are less expensive in terms of the amount of time required to perform them than other checks.

Abstract: A variational inference engine for probabilistic graphical models is disclosed. In one embodiment, a method includes inputting a specification for a model that has observable variables and unobservable variables. The specification includes a functional form for the conditional distributions of the model, and a structure for a graph of model that has nodes for each of the variables. The method determines a distribution for the unobservable variables that approximates the exact posterior distribution, based on the graph's structure and the functional form for the model's conditional distributions. The engine thus allows a user to design, implement and solve models without mathematical analysis or computer coding.

Abstract: A computer-implemented system analyzes user-inputted hypothetical situations of an electrical distribution network design and automatically interprets, based on user input, a need to conduct analyses that improve reliability of the electrical distribution network. The computer-implemented system includes a storage device configured to store different configurations of the distribution network, data corresponding to elements of the distribution network, and a set of engineering analysis modules. The computer-implemented system includes a controller configured to display and use a graphical user interface (GUI) to prompt a user to answer one or more questions about the distribution network. The controller is configured to receive answers and data from the user and retrieve data corresponding to elements of the distribution network. Then, the controller automatically selects and runs one or more of the engineering analysis modules based on the received answers.