Abstract: An epitaxial stack (10) is provided that allows integration of both vertical and horizontal quantum effect devices. Epitaxial stack (10) allows fabrication of both quantum well resonant tunneling transistors (27) and Stark-effect transistors (34), thus allowing for circuit integration of different quantum effect devices in the same epitaxial stack.

Abstract: A method is provided for planarizing a multi-layer metal bonding pad. A first metal layer (13) is provided. A first dielectric layer (14) is provided with a multitude of vias (17) covering the first metal layer (13), thereby exposing portions of the first metal layer (13) through the multitude of vias (17) in the first dielectric (14). A second metal layer (18) is deposited on the first dielectric layer (14) making electrical contact to the first metal layer through the multitude of vias (17). Planarization of the second metal layer (18) is achieved by having the second metal layer (18) cover the first dielectric layer (14) and making contact through the vias (17).

Abstract: A charge transfer device (CTD)/complementary metal oxide semiconductor (CMOS) process for the production of a signal processing apparatus is disclosed. The process consists of selectively combining virtual phase CCD process technology with CMOS technology to provide high density signal processing utilizing small (3 micron) geometries, sized P and N MOS (CMOS) transistors, and high valued (0.8 picofarad) poly-poly capacitors. The process is a single and efficient (14-16 photomasks) fabrication process starting with a single layer of P+ silicon as a substrate supporting an epitaxial layer of P silicon as the active area. An N well is formed in the epitaxial surface for a P-channel MOSFET, then using a patterned moat and positive and negative resists boron is ion implanted to form channel separators between N and P channel transistors, and P+ isolation regions and channel stops for the CCDs.

Abstract: A method for producing a hybrid integrated circuit includes steps of: applying an adhesive to an electronic part mounting conductor on an insulating substrate; adhering an electronic part to the applied adhesive and hardening the adhesive to temporarily fix the electronic part; fixing the temporarily fixed electronic part on the conductor with solder; and dissolving the hardened adhesive in a solvent and removing it. Upon being hardened, the adhesive can withstand the heat of molten solder and can be dissolved in a solvent and removed therewith.

Abstract: The use of an organic material having a conjugated ring system such as 3,4,9,10-perylenetetracarboxylic dianhydride interfaced with a semiconductor material such as silicon yields quite acceptable rectifying properties. These properties are used to test the suitability of the substrate during processing. Additionally, these materials upon irradiation change refractive index, allowing production of optical devices such as gratings. The combination of electrical and optical devices formed using these organic materials also allows relatively simple fabrication of integrated opto-electronic structures.

Abstract: A method for fabrication of a buried field shield in a semiconductor substrate. A seed substrate is prepared by depositing an epitaxial layer or a seed wafer and then depositing a heavily doped layer and a thin dielectric. The thin dielectric is patterned for contact holes and then a conductive field shield is deposited and patterned. A thick quartz layer is deposited over the field shield and dielectric. A mechanical substrate is anodically bonded to the quartz of the seed substrate and the original seed wafer is etched back to expose the epitaxial layer for further fabrication.

Abstract: Using a process in accordance with the teachings of this invention, an integrated circuit may be fabricated providing refractory metal silicide layers, such as TiSi.sub.2, of differing thicknesses to provide optimal reductions in the sheet resistances of the regions in which refractory metal silicide layers are formed. In one embodiment of the present invention a field effect transistor having a polycrystalline silicon gate is fabricated to provide a gate having optimally minimized sheet resistance and source and drain regions having TiSi.sub.2 layers of the appropriate thickness to avoid punch-through leakage problems.

Abstract: A semiconductor device is disclosed which includes an electrode or wiring layer having a polycrystalline silicon layer formed on an insulating film and a metal silicide layer formed thereon for reduction in electrical resistance. In order to prevent the metal silicide layer from diffusing into the polycrystalline silicon layer to finally reach the interface with the insulating film through various high-temperature heat treatment processes, the impurity concentration of the polycrystalline silicon layer is made different in the depthwise direction such that the concentration is higher at the lower part in contiguous with the insulating film than the upper part. With this structure, the diffusion of the metal silicide going to approach the insulating film is blocked by the presence of the lower part of high impurity concentration.