Abstract: A mesh connected local area network provides automatic packet switching and routing between host computers coupled to the network. The network has a multiplicity of cut-through, nonblocking switches, each capable of simultaneously routing a multiplicity of data packets. Low host-to-host latency is achieved through the use of cut-through switches with separate internal buffers for each packet being routed. The switches are interconnected with one another and are coupled to the host computers of the network by point to point full duplex links. While each switch can be coupled to ten or more network members, i.e., switches and hosts, each link is coupled to only two network members and is dedicated to carrying signals therebetween. Whenever a new switch or link is added to the network, and whenever a switch or link fails, the switches in the network automatically reconfigure the network by recomputing the set of legal paths through the network.

Abstract: A synchronous time division multiplexing system for multi-channel calls involves dividing each frame into a first segment and a second segment each containing substantially the same number of time slots and dividing the number of channels of the multi-channel call into a first subset and a second subset each containing approximately the same number of channels. Thereafter, the first subset is assigned to the first segment of the first frame and the second subset to the second segment of the first frame. The invention involves in a first time switching stage transposing the first subset to the second segment of the first frame such that the channels within the first subset occupy eligible free slots and retain their relative order and transposing the second subset to the first segment of the next frame such that the channels within the second subset occupy eligible free slots and retain their relative order. The call subsets are thus transported during a single stage of time switching.

Abstract: A link interface to a high-speed asynchronous multiplexed ATM telecommunication link includes a data segmenter for forming ATM cells out of data frames, and a data assembler and state memory for assembling data frames out of received multiplexed (interleaved)ATM cells. A novel architecture implemented in hardware, and characterized by absence of intermediate storage of data in the data segmenter and pipelined operation of the data assembler, allows the link interface to operate at hundreds of Megabits and Gigabits per second.

Abstract: A digital communication network (10) with a multiple space storage, time space-time configuration defined by a first, or input, time stage (12), a second, or output, time stage (14) and a preselected number of space stages (16, 22, 24) interconnected between the time stages 12, 14) that introduce time delays which are compensated for by means for time shifting the data in a shadow memory (32) relative to data in a regular memory (34). On-line expansion is accomplished by operating the network (10) off of one of the regular memory and the shadow memory (32) during the expansion, introducing the amount of compensation required by the expansion and then shifting operation over to the other memory. The selection between memories (34, 32) is achieved by means of a trislatable device (38).

Abstract: A system for controlling one or more groups of remotely located sensors, such as those capable of sensing environmental hazards, and reporting the findings of each group of sensors through a microcontroller back to a host computer for recording and warnings. The host computer polls each microcontroller over a radio link. Upon being polled, a microcontroller generates a return message identifying itself and providing the desired information from those sensors connected to it. The microcontrollers essentially identical, being designed to interface with many commercially available and/or special sensors. Normally, a sensor is connected to a microcontroller by an electrical or fiber optic line. The microcontroller can turn power to certain sensors on and off to conserve battery power and sound local alarms when requested to do so by the host.

Abstract: The invention discloses a single competitor arbitration code for determining if only one communications module is contending for a communication data bus and gives that module access within two bus clock cycles. An aggregate code is generated by using the true and complement of the module ID. A check code for each bit is determined by adding the aggregate code for the bit and its adjacent bit. If the check code contains any zeros, then more than one module is contending for the bus. The 10-bit single arbitration scheme allows for error detection and correction on a 32-bit data bus.

Abstract: A synchronous communication system includes a plurality of node elements and at least one two-way transmission line.

Abstract: Method and apparatus for controlling traffic flow in a wideband integrated services digital network including an asynchronous time division multiplexed switch network and a plurality of terminals operating at various data rates and providing different types of service. Control of traffic flow in the network is achieved by delaying data cells or allowing them to be lost, within limits that are predetermined as a function of the type of service provided by the terminals.

Abstract: Resequencing system for a switching node (SN) of a cell switching system wherein cells or packets, of fixed or variable length, transmitted from an input to an output of a switching network (SNW), are subjected in the network to variable initial time delays for instance because they follow different paths therein. To restore at the output the sequence with which the cells were supplied to the input the cells at the output are subjected to additional variable complementary time delays which are so chosen that for each cell the sum of the two time delays is substantially equal to a predetermined total value.

Abstract: A switching system for handling a plurality of cells, each cell including a header section and a data section, and for exchanging a communication message contained in the data section of the cell between a plurality of incoming highways and a plurality of outgoing highways according to the data contained in the header section of the cell. The switching system includes a unit for multiplexing the incoming highways in time division, a first memory having addressable storage locations for storing cells received from the multiplexing unit, a unit for demultiplexing and distributing data output from the first memory among a plurality of outgoing highways, a second memory for storing an empty address of an empty storage location of the first memory, a unit for controlling the write and read operations of the first memory in accordance with an empty address stored in the second memory used as write and read addresses, and a unit for detecting an error in at least one of the write address and read address.

Abstract: In a computer system having a host computer connected to one or more personal computers, a data transport system sends data back and forth between the host computer and the personal computers. Individual applications on a personal computer utilize resources on the host computer by use of a requester process existing on the personal computer. The requester process translates or reformats commands and associated information for sending to the host computer. A host server oversees the execution of such commands received by the host computer, and may call database intrinsics, operating system intrinsics, or remote procedure intrinsics to obtain execution of the command.

Abstract: An improved bi-directional buffer line amplifier is disclosed that provides a high performance analog interface between a Digital Network Interface Circuit (DNIC) and a transmission line. The buffer line amplifier includes a transmit amplifier network including an input connected to a DNIC transmit signal output. The input is arranged to receive transmit signals from the DNIC. A transmit output is connected to a matching network via a selectable gain amplifying circuit. The selectable gain amplifying circuit applies the transmit signals to the matching network in a first or a second gain level. In the first gain level the gain amplifying circuit is removed from the transmit amplifier network and the transmit amplifier network operates as a unity gain amplifier. This allows the buffer line amplifier to work efficiently with transmission line loop lengths from zero to a nominal distance.

Abstract: The method for providing an efficient and adaptive management of message routing in a multi-platform, communication system having dynamically changing platform populations and dynamically changing connectivities between platforms where each of the platforms are capable of performing the steps of recognizing at least certain ones of the platforms in the system, deriving from at least one of the recognized platforms the quality of interconnectivities of the recognized platforms and certain others of the platforms in the system; and employing the derived quality of interconnectivities to make connectivity-based routing decisions using a selective one of a point-to-point routing algorithm, a point-to-multipoint routing algorithm and a broadcast routing algorithm.

Abstract: A packet format for accurately transporting signaling information in a packet network is described. The packet format comprises a burst count, a sequence number, a burst time, and a signaling status bit. The burst count is for indicating a burst to which the packet belongs. The sequence number is for identifying a first packet of the burst. The burst time is for selectably indicating (1) a time delay from onset to a packet node bus for the first packet of the burst and (2) a time interval between successive signaling bit transitions.

Abstract: In a frame aligner for frame aligning an input time-division multiplexed (TDM) signal to an output frame synchronous signal, an input frame signal of the TDM signal is separated into a transport overhead carrying an input frame synchronous signal and a message pointer and a subframe carrying data signal. A fresh overhead having a fresh pointer is made corresponding to a phase difference between said input and said output frame synchronous signals and said subframe is sequentially written into and read from a buffer memory. The fresh overhead and the subframe read are multiplexed to form an output TDM frame signal which is synchronized with the output frame synchronous signal. The buffer memory is permitted to have a reduced memory capacity storable a number of channel signals equal to that of time slots carrying the overhead.

Abstract: A hand-held instructional device and a method of data selection is disclosed. Indexed information is stored in ROM and retrieved to an LCD display. Retrieval is by pressing keys with associated indicia indicating broad subsets of the information, consulting a displayed index of the subset, and pressing further keys as indicated by the index to display the desired sub-area of the subset. Scrolling is provided to allow multiple screens of information to be reviewed. Both automatic and manual scrolling is used. An embodiment of the invention where the information stored is welding and cutting information is disclosed. A calculator operation is included to allow the user to manipulate the welding and cutting data for the job at hand.

Abstract: A digital cellular time-division multiple access (TDMA) system including a cellular switch and at least one base site employing 6:1 packing of transcoded information. The system incorporates the VSELP speech encoding algorithm to transcode data input from a cellular switch and a unique packing scheme to compress six messages channels worth of transcoded data into one 20 msec, 160 frame information block for transmission in one TDM timeslot. The compressed transcoded data is transmitted to a base-site on a T1 link where the six message channels worth of transcoded data is un-packed and coded. The coded information is then separated into two groups of three air-interface timeslots where two separate transmitters transmit one group each of three air-interface timeslots on two separate radio carrier frequencies.

Abstract: A storage star network for providing maximum propagation delay includes a plurality of terminal stations and a toll center for routing data packets among the stations. Each terminal station includes a memory and each data packet has an associated priority.

Abstract: A data transfer control apparatus for a co-processor system. The co-processor system includes a memory; a memory bus connected to the memory; a main processor connected to the memory bus and having a control circuit for controlling data read/write relative to the memory, the main processor performing data transfer from/to the memory bus via a first data input/output terminal; and a co-processor connected to the memory bus via a second data input/output terminal. The control apparatus includes a high impedance setting circuit for selectively setting the first data input/output terminal at a high impedance state to electrically isolate the first data input/output terminal from the memory bus; and a control signal generator for selectively outputting a control signal to the high impedance setting circuit to cause the high impedance setting circuit to set the first data input/output terminal at the high impedance state.

Abstract: There is disclosed a collision filter for use in a network to detect a fault condition wherein two or more nodes are simultaneously transmitting on the network. The fault condition is characterized by an increased average DC voltage level on the network. The collision filter includes a low pass filter stage having an input coupled to the network and an output and a notch filter having an input coupled to the low pass filter stage output. The notch filter has at least one attenuation notch at a desired frequency and an output for providing the increased average DC voltage level responsive to a fault condition.