Abstract: A matrix form semiconductor package substrate that has an electrode situated in-between a plurality of IC package substrates for providing electrical communication to conductive pads on the substrate is provided. The matrix form semiconductor package substrate includes a plurality of IC package substrates that are integrally formed on a strip in a matrix pattern that has a boundary between each two of the plurality of IC package substrates. Each of the plurality of IC package substrates has a multiplicity of conductive pad traces and an electrode, or a plating bar, formed in a serpentine configuration along the boundary for providing electrical communication to the multiplicity of conductive pads.

Abstract: Alignment marks are formed when source and drain electrodes of a TFT are formed and thereon a thick red filter in formed. So that, the following respective color layers can be made thin on the red filter. Also, the exposure alignment laser permeates in an exposure step, and thereby the alignment marks can be accurately detected.

Abstract: A method of making a heterojunction bipolar transistor comprises the steps of: forming a mask layer on a compound semiconductor film by using a photomask for forming an emitter; and forming the emitter by wet-etching the compound semiconductor film by using the mask layer. The photomask has a pattern thereon for forming the emitter. The pattern is defined by a first area R associated with the shape of the emitter to be formed, and a plurality of second areas T1 to T4. Each of the second areas T1 to T4 includes first and second sides S1 and S2 meeting each other to form an acute angle therebetween, and a third side S3 in contact with the first area R. In each of the second areas T1 to T4, one side S3 of the two sides meeting each other to form a right angle therebetween is in contact with one side of the area R, whereas the other side S1 is connected to another side of the first area R to form a line segment.

Abstract: There is provided is a metal line structure in which no defect of blistering occurs on a surface of a Cu/Ni film or a Cu/Au/Ni film even if an Ni plating thickness is reduced. According to this metal line 1, in a Cu/Au/Ni film structure in which an Au film 13 and a Cu film 15 are successively laminated by electroless plating on an Ni film 12 formed by electroless plating, the Ni film 12 has a phosphorus content x of 10 wt %≦x≦15 wt %. It was discovered through experiments that the so-called high phosphorus content type Ni film 12 having a phosphorus content x of 10 to 15 percent by weight became a fine smooth film under a condition of a film thickness of 0.1 &mgr;m or greater.

Abstract: A grating based line narrowing unit with bi-directional beam expansion for line narrowing lasers. In a preferred embodiment a beam from the chamber of the laser is expanded in the horizontal direction with a three-prism beam expander and is expanded in the vertical direction with a single prism. A narrow band of wavelengths in the expanded beam is reflected from a grating in a Littrow configuration back via the two beam expanders into the laser chamber for amplification.

Abstract: A semiconductor light receiving element having a light receiving layer (1) formed from a GaN group semiconductor, and an electrode (2) formed on one surface of the light receiving layer as a light receiving surface (1a) in such a way that the light (L) can enter the light receiving layer is provided. When the light receiving element is of a Schottky barrier type, the aforementioned electrode (2) contains at least a Schottky electrode, which is formed in such a way that, on the light receiving surface (1a), the total length of the boundary lines between areas covered with the Schottky electrode and exposed areas is longer than the length of the outer periphery of the light receiving surface (1a).

Abstract: A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.

Abstract: A method for manufacturing a three-dimensionally structured vertical transistor or memory cell forms a silicon-on-insulator (SOI) structure on a semiconductor substrate and sequentially deposits a drain region, a channel region and a source region on the SOI substrate structure. The transistor includes a cylinder-type gate insulation layer surrounding the channel region and a gate electrode surrounding the gate insulation layer, having increased integration. This process and structure avoid the characteristic degradation caused by the leakage current associated with the trench process and structure.

Abstract: In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is connected to a second interconnect level by the interlevel connector (14), and the perimeter (22) of the interlevel connector (14) is located at the juncture between the first interconnect level (12) and the interlevel connector (14). The first interconnect level (12) has two or more fingers (16,18,20) protruding therefrom that connect to the perimeter (22) of the interlevel connector (14). At least one opening (36, 38) is disposed between two of the fingers (16,18,20) for dividing current flow.

Abstract: A semiconductor device used as a semiconductor memory device is disclosed which is made of an amorphous silicon material that provides either a "1" or "0" memory state when the amorphous silicon material is in a non-conduction or insulating state and a "0" or "1" memory state when the amorphous silicon material is transformed, by use of a breakdown voltage applied to electrodes coupled thereto, into a conducting state. The amorphous silicon material is located adjacent to a doped semiconductor region of a semiconductor substrate separated only by a relatively thin primarily metal ohmic contact. The resulting semiconductor structure for the semiconductor device or semiconductor memory device is primarily a single level metalization type structure. A write-once, read-only semiconductor memory array is also disclosed which uses, as each memory cell of the array, one of the disclosed semiconductor memory devices.

Abstract: A method of manufacturing a semiconductor device is set forth, comprising a silicon body (1) having a surface (4) where there are situated a number of semiconductor regions (5, 6) and field oxide regions (7). The semiconductor regions is formed, after the field oxide regions have been provided, by implantations of n-type and p-type dopants. In accordance with the invention the implantations with the n-type dopant (10, 11, 14), which are performed using an implantation mask (8) provided on the surface and comprising openings (9) at the area of a part of the semiconductor regions (5) to be formed, are combined with the implantations with the p-type dopant (12, 13, 15) which are carried out without using the implantation mask. Thus, the semiconductor regions (5, 6) are realised by means of a single implantation mask (8).

Abstract: A semiconductor memory device comprises a p.sup.- -type semiconductor substrate (1), p.sup.+ -type regions (15, 80) formed thereon, n.sup.+ -type regions (6, 7) surrounded with the p.sup.+ -type regions (15, 80), a first gate electrode (2) formed on a charge storage region in the n.sup.+ -type region (6), and a second gate electrode (3) formed on the p.sup.+ -type region (80) and serving as a word line. The p.sup.+ -type regions (15, 80) prevent passage of electrons out of electron-hole pairs induced by alpha rays so as to prevent occurrence of soft errors. An oxide film (16) is formed on the side wall of the second gate electrode (3), a titanium silicide film (17) is formed on the n.sup.+ -type regions (6, 7) and a titanium silicide film (18) is formed on the second gate electrode (3) in a self-aligning manner. Therefore, increase of interconnection resistance of the second gate electrode (3 ) and diffusion resistance of the n.sup.+ -type regions (6, 7) is prevented.

Abstract: A BIC memory cell device comprises a first insulating layer covering a MOS structure, a first penetrating opening in the first insulating layer in correspondence to a drain region and defined by an inclined first side wall which defines the diameter of the first opening such that the diameter increases towards a top surface of the first insulating layer, a second penetrating opening in the first insulating layer in correspondence to a source region and defined by a second side wall having a straight vertical cross section, a third penetrating opening in the first insulating layer in correspondence to a gate electrode and defined by a third side wall having a straight vertical cross section, a second insulating layer provided on the first insulating layer in correspondence to the drain region, a first wiring electrode deposited such that the second insulating layer is sandwiched between the first wiring electrode and the drain region, and second and third wiring electrodes contacting with the source region and

Abstract: In a semiconductor memory integrated circuit device having a stacked capacitor cell, a first plate electrode and a first dielectric film are formed underneath a charge storage electrode a charge storage electrode, and a second dielectric film and a second plate electrode are formed over the charge storage electrode. The charge storage electrode has contact with the diffusion region through a contact hole penetrating the first dielectric material. The first and second plate electrodes are connected via a contact hole penetrating the first and second electric films outside the cell area. Because both the upper surface and the lower surface of the charge storage electrode are utilized for formation of the capacitor the size of the capacitor can be halved to produce the same capacitance.

Abstract: An electrically programmable non-volatile memory comprises word lines (LM2) extending along rows, and bit lines (LB1) extending along columns. Each memory point (PM1) is constituted by a pair of MOS transistors (T22, T23) having a floating gate (23). A conductive area (25) is connected to the floating gates (23) of the two transistors (T22, T23) of each pair and is in register with the word line (LM2) connected to the memory point (PM1) made by the transistor pair. This word line (LM2) corresponds, at the position of this pair, to the control gate (28).

Abstract: In the semiconductor memory device according to the present invention, a n type drain diffused region (9a) to be connected to a bit line (12) is formed on a p type semiconductor substrate (1) and a n type source diffused region (9b) is formed with a prescribed spacing from the n type drain region (9a). On the p type silicon substrate (1), a p type diffused region (16a) of high impurity density and p type diffused region (16b) of high impurity density are formed in such a manner that they are in contact with the n type drain diffused region (9a) and the n type source diffused region (9b), respectively, but not in the channel region of the n channel MOS transistor (18). Consequently, the .alpha. particle-generated charges can be decreased without changing the threshold voltage of the transfer gate transistor.

Abstract: A semiconductor integrated circuit device having a wiring line of aluminum film or aluminum alloy film covered with a silicon insulation film and connected to the semiconductor region formed on the principal surface of a single crystal silicon substrate, with a polycrystalline silicon film interposed, wherein said silicon film is a polycrystalline silicon film composed of large crystal grains which is formed by depositing in amorphous state and then heat-treating the deposited film, said polycrystalline silicon film reduces the amount of silicon atoms which separates out in said wiring line. Also said wiring line is provided with a shielding film which is disposed between said insulation film and at least the upper surface and lower surface of said wiring line and which prevents silicon atoms from separating out from said insulation film.

Abstract: The described embodiments of the present invention provide DRAM cells, structures and manufacturing methods. A DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. The transfer transistor is formed using a field plate isolation structure which includes a self-aligned moat area for the transfer transistor. The moat area slightly overlaps the capacitor area and allows for increased misalignment tolerance thus foregoing the requirement for misalignment tolerances built into the layout of the DRAM cell. The field plate itself is etched so that it has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers formed on the integrated circuit.

Abstract: In a semiconductor fabrication technique, a first patterned layer (16) of nonmonocrystalline semiconductor material is created on a substructure (10, 12, 14). An insulating layer (22) is thermally grown along the patterned layer in such a way that the upper edge of the remainder (16A) of the patterned layer forms an asperity (24). A blanket layer 26, preferably consisting of nonmonocrystalline semiconductor material, is formed over the insulating layer. Using an etchant that attacks the blanket and patterned layers more than the insulating layer, a selective etch is performed to remove a section of the blanket layer. The etch is continued past the blanket layer to remove the underlying portion of the insulating layer located along the asperity and then, importantly, to remove the so exposed part of the asperity. The remainder (26A) of the blanket overlies the remainder ( (24A) of the asperity.

Abstract: A capacitor is formed for use with a DRAM storage cell by lying down alternating layers of polycrystalline silicon for the storage node and the ground plate. A buried bit line allows the capacitor area to cover a significant fraction of the cell layout area. The alternating storage node and ground plates of the capacitor are laid down alternately, and connected together as they are formed. The number of interleaved layers which can be used to form the capacitor can easily be varied to suit process requirements.